zl50075 Zarlink Semiconductor, zl50075 Datasheet - Page 41

• Manufacturer Part Number: zl50075
• Description: 32 K Channel Digital Switch With High Jitter Tolerance, Rate Conversion Per Group Of 2 Streams 8, 16, 32 Or 64 Mbps , And 64 Inputs And 64 Outputs
• Manufacturer: Zarlink Semiconductor

The Group Control Register is a static control register. Changes to bit settings may disrupt data flow on the selected
port for a maximum of 2 frames.
3 - 2
1 - 0
External Read/Write Address: 40200
Reset Value: 000C000C
Bit
31
15
0
0
30
14
0
0
ISSRC1 - 0
ISBR1 - 0
Name
29
13
0
0
28
12
0
0
H
27
11
Input Stream Bit Rate
Unused streams must be connected to ground.
If the internal system clock is used as the clock source, all the above data rates are
available. Otherwise, the data rate cannot exceed the selected clock source’s rate.
Input Stream Clock Source Select
0
0
Table 23 - Group Control Register (continued)
H
ISBR1 - 0
ISSRC1 - 0
26
10
- 4027F
0
0
00
01
10
11
00
01
10
11
25
ISI
0
9
H
ISPD
24
8
Zarlink Semiconductor Inc.
0
4
16.384 Mbps
32.768 Mbps
65.536 Mbps
8.192 Mbps
ZL50075
STiA
ISPD
Bit Rates Per Group
23
7
0
3
Internal System Clock
Input Timing Source
41
CKi0 and FPi0
ISPD
OSI
22
Reserved
Reserved
6
2
Description
16.384 Mbps
32.768 Mbps
8.192 Mbps
OSBA
Not Used
ISPD
21
5
1
1
STiB
OSBA
ISPD
20
4
0
0
OSBR
ISBR
19
1
3
1
OSBR
ISBR
18
0
2
0
OSSRC
ISSRC
17
1
1
1
Data Sheet
OSSRC
ISSRC
16
0
0
0