zl50075 Zarlink Semiconductor, zl50075 Datasheet - Page 23

• Manufacturer Part Number: zl50075
• Description: 32 K Channel Digital Switch With High Jitter Tolerance, Rate Conversion Per Group Of 2 Streams 8, 16, 32 Or 64 Mbps , And 64 Inputs And 64 Outputs
• Manufacturer: Zarlink Semiconductor

Each PRBS detector can be configured to monitor for bit errors in one or more timeslots. The selection of timeslots
is configured by the Input BER Enable Control Memory (IBERECM). See Section 14.3.1 for programming details,
Each detector has an associated 16 bit error counter accessible via the microprocessor interface, as described in
Section 14.3.2, BER Counters. The value of the counter represents the total number of errors detected on the
corresponding input stream. Bit errors are accumulated until the counter is either reset (by writing to the counter or
by resetting the device), or the counter reaches its maximum value, 65,535 (decimal). If more than 65,535 errors
are detected, the counter will hold at the maximum value until reset.
Any number of timeslots may be configured for bit error rate testing; however the user must ensure the following for
correct operation of the BER test function:
1. The number of timeslots enabled for PRBS detection on the input stream must equal the number of timeslots
2. The arrival order of timeslots at the PRBS detector must be the same as the order in which timeslots were trans-
10.0
The ZL50075 has a generic 16-bit microprocessor port that provides access to the 32-bit internal Data Memory
(read access only), Connection Memory and Control Registers. D15 on the bus maps to Bit 31 and Bit 15 of the
internal 32 bit memory or register, D14 maps to Bit 30 and Bit 14, etc.
The IM pin is used to select between Motorola bus control and Intel bus control. If the IM input is low, then a
Motorola control is selected. If the IM bit is high, then an Intel control is selected. Regardless of which bus
configuration is selected, the bus cycle termination signals WAIT & DTA are both provided.
The Data Memory, Connection Memory and Control Registers are assigned 32 bit fields in the ZL50075 memory
space. Each 32 bit memory or register location spans 4 consecutive addresses. Example:
•
The Least Significant address identifies the Most Significant Byte (MSB) in the 32 bit field, as illustrated in Table 5.
enabled for PRBS generation on the source output stream
mitted by the PRBS generator. For example, in Figure 8 above, the timeslot order a, b, c must be maintained
through the external path from source TDM output stream to destination TDM input stream.
The 32 bit Group Control Register for TDM Group 0 is located at address range 40200 - 40203 Hex
Microprocessor Port
..010111001101101111001010110110001011111011010011100001101...
a
Frame m
b
Figure 8 - Example PRBS Timeslot Insertion
c
Zarlink Semiconductor Inc.
ZL50075
23
Example segment of serial bit pattern
from Stream N PRBS Generator
a
Frame m+1
b
c
Stream N with Channels
for PRBS insertion
a, b and c enabled
Data Sheet
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