r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 806
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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16. Watchdog Timer and Reset (WDT)
(3)
It is necessary to ensure the PLL oscillation settling time when a power-on reset is initiated by a
low level input on the PRESET pin during sleep mode.
The timing of reset state indication on the STATUS[1:0] pins is asynchronous. The timing of
indicating normal operation is synchronous with the peripheral clock (Pck), and is therefore
asynchronous with the clocks input from the EXTAL pin and the CLKOUT pin.
Rev.1.00 Jan. 10, 2008 Page 776 of 1658
REJ09B0261-0100
EXTAL
input
CLKOUT
output
CLKOUTENB
output
PRESET
input
STATUS[1:0]
output
Power-On Reset Caused by PRESET Input in Sleep Mode
Figure 16.5 STATUS Output by Power-On Reset Caused by PRESET Input
HL (sleep)
HH (reset)
PLL oscillation
settling time
in Sleep Mode
HH (reset)
Reset holding time
LL (normal)
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