r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 221
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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7.7.1
The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and VPN, V, and ASID to be written to the address array are
specified in the data field.
In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array and the
entry is specified by bits [9:8]. As only longword access is used, 0 should be specified for address
field bits [1:0].
In the data field, bits [31:10] indicate VPN, bit [8] indicates V, and bits [7:0] indicate ASID.
The following two kinds of operation can be used on the ITLB address array:
1. ITLB address array read
2. ITLB address array write
VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry
set in the address field.
VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to
the entry set in the address field.
ITLB Address Array
Address field
Data field
Figure 7.18 Memory-Mapped ITLB Address Array
31
31
1 1 1 1 0 0
VPN:
V:
E:
*:
Virtual page number
Validity bit
Entry
Don't care
1 0
24
23
* * * * * * * * * * * * *
VPN
ASID:
:
Address space identifier
Reserved bits (write value should be 0,
and read value is undefined )
Rev.1.00 Jan. 10, 2008 Page 191 of 1658
10 9 8 7
10 9
7. Memory Management Unit (MMU)
9 8 7
E
V
* * * * * *
ASID
2 1
REJ09B0261-0100
0 0
0
0
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