r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1368
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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27. NAND Flash Memory Controller (FLCTL)
(5)
• On-chip 224-byte FLDTFIFO for data transfer of flash memory
• On-chip 32-byte FLECFIFO for data transfer of a control code
• Flag bit for detection of overrun or underrun during access from the CPU or DMA
(6)
• By individually specifying the transfer destinations of data and control code of flash memory
(7)
• Registers include 32-bit registers and an 8-bit register. Read from or write to the register with
• The access size of FIFO is 32 bits (4 bytes). In reading, set the byte number to a multiple of
(8)
• The operating frequency of the FLCTL pins can be specified by the FCKSEL bit and the
• The operating clock, FCLK, on the pins for the NAND-type flash memory is used by dividing
• In NAND-type flash memory, the FRE and FWE pins operate with the FCLK specified by
Rev.1.00 Jan. 10, 2008 Page 1338 of 1658
REJ09B0261-0100
to the DMA controller, data and control code can be transferred to different areas.
the specified access size.
four. In writing, set the byte number to a multiple of four in writing.
QTSEL bit in FLCMNCR, regardless of the operating frequency of the peripheral bus.
the operating clock of the peripheral bus (a peripheral clock).
FLCMNCR. To ensure the setup time, this operating frequencies should not exceed the
maximum operating frequency of memory to be connected.
Data Transfer FIFO
DMA Transfer
Access Size
Access Time
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