r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 483
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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Company:
Part Number:
r8a77850anbgV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 11.19 Register Settings for Divided-Up DACKn Output in DMA1 Transfer Using the
Note: "⎯" means an arbitrary setting value. When transfer is done in a single bus cycle, DACKn
Bus Width
[Bit]
8
16
32
64
is not divided up because DACKn is output once in DMA1 transfer.
Access Size in
DMA Transfer
Byte
Word
Longword
16 bytes
32 bytes
Byte
Word
Longword
16 bytes
32 bytes
Byte
Word
Longword
16 bytes
32 bytes
Byte
Word
Longword
16 bytes
32 bytes
SRAM/Burst ROM/Byte Control SRAM Interfaces
Bus Cycle
Number
1
2
4
32
1
1
2
16
1
1
1
8
1
1
1
4
16
8
4
4
IWRRD, IWRRS, or
IWW in CSnBCR
⎯
⎯
⎯
B'000
⎯
⎯
⎯
⎯
B'000
⎯
⎯
⎯
⎯
B'000
⎯
⎯
⎯
⎯
B'000
⎯
Not Divided
Rev.1.00 Jan. 10, 2008 Page 453 of 1658
11. Local Bus State Controller (LBSC)
ADS and ADH in
CSnWCR.
⎯
B'000
B'000
B'000
B'000
⎯
⎯
B'000
B'000
B'000
⎯
⎯
⎯
B'000
B'000
⎯
⎯
⎯
B'000
B'000
REJ09B0261-0100
Divided
ADS and ADH
inCSnWCR
Undividable
B'111 to B'001
B'111 to B'001
B'111 to B'001
B'111 to B'001
Undividable
Undividable
B'111 to B'001
B'111 to B'001
B'111 to B'001
Undividable
Undividable
Undividable
B'111 to B'001
B'111 to B'001
Undividable
Undividable
Undividable
B'111 to B'001
B'111 to B'001
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