r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1100
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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21. Serial Communication Interface with FIFO (SCIF)
21.3.14 Serial Error Register n (SCRER)
SCRER is a 16-bit register that indicates the number of receive errors in the data in SCFRDR.
SCRER can always be read from the CPU.
Rev.1.00 Jan. 10, 2008 Page 1070 of 1658
REJ09B0261-0100
Initial value:
Bit
15, 14
13
12
11
10
9
8
7, 6
5
4
3
2
1
0
R/W:
BIt:
Bit Name
—
PER5
PER4
PER3
PER2
PER1
PER0
—
FER5
FER4
FER3
FER2
FER1
FER0
15
⎯
R
0
14
⎯
R
0
PER5
13
R
0
Initial
Value
All 0
0
0
0
0
0
0
All 0
0
0
0
0
0
0
PER4
12
R
0
PER3
11
R
0
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
PER2
10
R
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Parity Errors
These bits indicate the number of data bytes in which a
parity error occurred in the receive data stored in
SCFRDR.
After the ER bit in SCFSR is set, the value indicated by
bits PER5 to PER0 is the number of data bytes in
which a parity error occurred.
If all 64 bytes of receive data in SCFRDR have parity
errors, the value indicated by bits PER5 to PER0 is 0.
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Framing Errors
These bits indicate the number of data bytes in which a
framing error occurred in the receive data stored in
SCFRDR.
After the ER bit in SCFSR is set, the value indicated by
bits FER5 to FER0 is the number of data bytes in which
a framing error occurred.
If all 64 bytes of receive data in SCFRDR have framing
errors, the value indicated by bits FER5 to FER0 is 0.
PER1
R
9
0
PER0
R
8
0
⎯
R
7
0
⎯
R
6
0
FER5
R
5
0
FER4
R
4
0
FER3
R
3
0
FER2
R
2
0
FER1
R
1
0
FER0
R
0
0
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