r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 307
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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Part Number:
r8a77850anbgV
Manufacturer:
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10.3.1
(1)
ICR0 is a 32-bit readable and partially writable register that sets the input signal detection mode
for the external interrupt input pins and NMI pin, and indicates the level being input on the NMI
pin.
Initial value:
Initial value:
Bit
31
30
29 to 26 ⎯
R/W:
R/W:
Interrupt Control Register 0 (ICR0)
Bit:
Bit:
External Interrupt Request Registers
Name
NMIL
MAI
NMIL
31
15
—
⎯
R
R
0
R/W
MAI
30
14
⎯
R
0
0
Initial
Value
Undefined R
0
All 0
29
13
⎯
⎯
R
R
0
0
28
12
⎯
⎯
R
R
0
0
27
⎯
11
⎯
R
R
0
0
R/W
R/W
R
26
10
⎯
⎯
R
R
0
0
Description
NMI Input Level
Indicates the signal level being input on the NMI pin.
Reading this bit allows the user to know the NMI pin
level, and writing is invalid.
0: Low level is being input on the NMI pin
1: High level is being input on the NMI pin
MAI (mask all interrupts) Interrupt Mask
Specifies whether all interrupts are masked while the
NMI pin is at the low level regardless of the setting of
the BL bit in SR of the CPU.
0: Interrupts remain enabled even when the NMI pin
1: Interrupts are disabled when the NMI pin goes low
Reserved
These bits are always read as 0. The write value
should always be 0.
NMIB
R/W
25
⎯
goes low
R
0
9
0
NMIE
R/W
24
⎯
R
0
8
0
IRLM0
R/W
23
⎯
R
0
7
0
IRLM1
Rev.1.00 Jan. 10, 2008 Page 277 of 1658
R/W
22
⎯
R
0
6
0
MODE
R/W
LVL
21
⎯
R
0
5
0
10. Interrupt Controller (INTC)
20
⎯
⎯
R
R
0
4
0
19
⎯
⎯
R
R
0
3
0
REJ09B0261-0100
18
⎯
⎯
R
R
0
2
0
17
⎯
⎯
R
R
0
1
0
16
⎯
⎯
R
R
0
0
0
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