mcimx27- Freescale Semiconductor, Inc, mcimx27- Datasheet - Page 87

• Manufacturer Part Number: mcimx27-
• Description: Multimedia Applications Processor
• Manufacturer: Freescale Semiconductor, Inc

3.6.11.3
Figure 49
parameters.
Freescale Semiconductor
and
Note: SRXD Input in Synchronous mode only
SSI Transmitter Timing with External Clock
Figure 50
All the timings for the SSI are given for a non-inverted serial clock polarity
(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the
polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing is the
same as that of Tx Data, for example, during the AC97 mode of operation.
SS49
SS50
SS51
Table 47. SSI Receiver with Internal Clock Timing Parameters (continued)
ID
AD1_TXFS (wl)
AD1_TXFS (bl)
(Input)
(Input)
AD1_RXD
AD1_TXD
(Output)
AD1_TXC
(Input)
(Input)
Figure 49. SSI Transmitter with External Clock Timing Diagram
Oversampling clock rise time
Oversampling clock low period
Oversampling clock fall time
show the SSI transmitter timing with external clock, and
SS23
SS27
Preliminary—Subject to Change Without Notice
i.MX27 and i.MX27L Data Sheet, Rev. 1.2
Parameter
SS22
SS31
SS37
SS29
NOTE
SS44
SS26
SS25
Min
—
—
6
SS38
SS45
SS24
Max
—
3
3
SS46
Table 48
SS39
Unit
ns
ns
ns
SS33
Signal Descriptions
lists the timing
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