mcimx27- Freescale Semiconductor, Inc, mcimx27- Datasheet - Page 53

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mcimx27-

Manufacturer Part Number
mcimx27-
Description
Multimedia Applications Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
HCLK = AHB System Clock, THCLK = Period of HCLK
3.5.6
This section describes the electrical information of the CSPI.
3.5.6.1
Figure 13
timing parameters.
Freescale Semiconductor
DATA[7:0]
PIXCLK
VSYNC
and
Number
Configurable Serial Peripheral Interface (CSPI)
Figure 12. CSI Timing Diagram, Non-Gated, PIXCLK—Sensor Data at Rising Edge,
CSPI Timing
Figure 14
csi_vsync to csi_pixclk
csi_d setup time
csi_d hold time
csi_pixclk high time
csi_pixclk low time
csi_pixclk high time
show the master mode and slave mode timings of CSPI, and
Table 22. Non-Gated Clock Mode Parameters
1
Parameter
Preliminary—Subject to Change Without Notice
i.MX27 and i.MX27L Data Sheet, Rev. 1.2
2
Latch Data at Falling Edge
Valid Data
3
Minimum
9*T
T
T
Valid Data
HCLK
HCLK
HCLK
1
1
0
5
Maximum
6
HCLK/2
4
Valid Data
Table 23
MHz
Unit
ns
ns
ns
ns
ns
Signal Descriptions
lists the
53

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