mcimx27- Freescale Semiconductor, Inc, mcimx27- Datasheet - Page 77

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mcimx27-

Manufacturer Part Number
mcimx27-
Description
Multimedia Applications Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Freescale Semiconductor
1
SD10 and SD11 are determined by SDRAM controller register settings.
SD10
SD11
SD6
SD7
ID
SDCLK
CAS
CKE
ADDR
RAS
WE
CS
Address setup time
Address hold time
Precharge cycle period
Auto precharge command period
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Don’t care
BA
Table 39. SDRAM Refresh Timing Parameters (continued)
Figure 40. SDRAM Self-Refresh Cycle Timing Diagram
Parameter
Table 39
1
Preliminary—Subject to Change Without Notice
SD16
i.MX27 and i.MX27L Data Sheet, Rev. 1.2
indicates SDRAM requirements. All output signals
1
NOTE
Symbol
tRC
tAS
tAH
tRP
SD16
Min
1.8
1.8
1
2
Max
20
4
Signal Descriptions
clock
clock
Unit
ns
ns
77

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