mcimx27- Freescale Semiconductor, Inc, mcimx27- Datasheet - Page 74

• Manufacturer Part Number: mcimx27-
• Description: Multimedia Applications Processor
• Manufacturer: Freescale Semiconductor, Inc

Signal Descriptions
74
1
Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see
Table 41
SD10
SD9
ID
and
Data out hold time
Active to read/write command period
Table
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Table 37. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
42.
1
Table 37
Preliminary—Subject to Change Without Notice
Parameter
i.MX27 and i.MX27L Data Sheet, Rev. 1.2
indicates SDRAM requirements. All output signals
NOTE
Symbol
tOH
tRC
Min
1.8
10
Freescale Semiconductor
Max
—
—
clock
Unit
ns