mcimx27- Freescale Semiconductor, Inc, mcimx27- Datasheet - Page 52

• Manufacturer Part Number: mcimx27-
• Description: Multimedia Applications Processor
• Manufacturer: Freescale Semiconductor, Inc

Signal Descriptions
For example: Given pixel clock period = 10 ns, duty cycle = 50/50, hold time = 1 ns, setup time = 1 ns.
Falling-edge latch data:
3.5.5.2
In non-gated mode only, the VSYNC, and PIXCLK signals are used; the HSYNC signal is ignored. Figure
3 and Figure 4 show the different clock edge timing of CSI and Sensor in Non-Gated Mode. Table 3 is the
parameter value.
lists the timing parameters.
Figure 11
rising edge.
Figure 12
falling edge.
52
positive duty cycle = 10/2 = 5 ns
max rise time allowed = 5 –1 = 4 ns
negative duty cycle = 10/2 = 5 ns
max fall time allowed = 5 –1 = 4 ns
max fall time allowed = (negative duty cycle
max rise time allowed = (positive duty cycle
VSYNC
PIXCLK
DATA[7:0]
shows sensor output data on the pixel clock falling edge. The CSI latches data on the pixel clock
shows sensor output data on the pixel clock rising edge. The CSI latches data on the pixel clock
Figure 11. CSI Timing Diagram, Non-Gated, PIXCLK—Sensor Data at Falling Edge,
Non-Gated Clock Mode Timing
Figure 11
and
1
Figure 12
Preliminary—Subject to Change Without Notice
i.MX27 and i.MX27L Data Sheet, Rev. 1.2
2
Valid Data
Latch Data at Rising Edge
show the non-gated clock mode timings of CSI, and
3
—
—
setup time)
hold time)
Valid Data
4
6
5
Valid Data
Freescale Semiconductor
Table 22