mcimx27- Freescale Semiconductor, Inc, mcimx27- Datasheet - Page 32

• Manufacturer Part Number: mcimx27-
• Description: Multimedia Applications Processor
• Manufacturer: Freescale Semiconductor, Inc

Signal Descriptions
32
SSI3_CLK
SSI3_TXD
SSI3_RXD
SSI3_FS
SSI4_CLK
SSI4_TXD
SSI4_RXD
SSI4_FS
TIN
TOUT1
Note: TOUT2, TOUT3 are multiplexed with PWMO pad; GPT4 and GPT5 signals are multiplexed with SSI2 pads.
USBOTG_DIR/TXDM
USBOTG_STP/TXDM
USBOTG_NXT/TXDM
USBOTG_CLK/TXDM
USBOTG_DATA7/SUSPEND
USBH2_STP/TXDM
USBH2_NXT/TXDM
USBH2_DATA7/SUSPEND
USBH2_DIR/TXDM
USBH2_CLK/TXDM
USBOTG_DATA3/RXDP
USBOTG_DATA4/RXDM
USBOTG_DATA1/TXDP
USBOTG_DATA2/TXDm
Pad Name
Table 3. i.MX27/MX27L Signal Descriptions (continued)
Serial clock signal which is output in master or input in slave. This signal is multiplexed with
SLCDC2_CLK; through GPIO multiplexed with PC_WAIT_B; PC31.
Transmit serial data signal which is multiplexed with SLCDC2_CS, through GPIO multiplexed
with PC_READY; PC30
Receive serial data which is multiplexed with SLCDC2_RS; through GPIO multiplexed with
PC_VS1; PC29
Frame Sync signal which is output in master and input in slave. This signal is multiplexed with
SLCDC2_D0; through GPIO multiplexed with PC_VS1; PC28.
Serial clock signal which is output in master or input in slave; through GPIO multiplexed with
PC_BVD1; PC19
Transmit serial data; through GPIO multiplexed with PC_BVD2; PC18
Receive serial data; through GPIO multiplexed with IOIS16; PC17
Frame Sync signal which is output in master and input in slave; PC16
Timer Input Capture or Timer Input Clock—The signal on this input is applied to GPT 1–3
simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL,
Clock, and Reset Controller module, and is also multiplexed with GPT6_TOUT; PC15.
Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with
SSI1_MCLK and SSI2_MCLK signal of SSI1 and SSI2. The pin name of this signal is simply
TOUT, and is also multiplexed with GPT6_TIN; PC14.
USB OTG direction/Transmit Data Minus signal, multiplexed with KP_ROW7A; PE2
USB OTG Stop signal/Transmit Data Minus signal, multiplexed with KP_ROW6A; PE1
USB OTG NEXT/Transmit Data Minus signal, multiplexed with KP_COL6A; PE0
USB OTG Clock/Transmit Data Minus signal, PE24
USB OTG Data7/Suspend signal, PE25
USB Host2 Stop signal/Transmit Data Minus signal, PA4
USB Host2 NEXT/Transmit Data Minus signal, PA3
USB Host2 Data7/Suspend signal, PA2
USB Host2 Direction/Transmit Data Minus signal, PA1
USB Host2 Clock/Transmit Data Minus signal; PA0
USB OTG data4/Receive Data Plus signal; multiplexed with SLCDC1_DAT15 through PC13
USB OTG data4/Receive Data Minus signal; multiplexed with SLCDC1_DAT14 through PC12
USB OTG data1/Transmit Data Plus signal; multiplexed with SLCDC1_DAT13 through PC11
USB OTG data2/Transmit Data Minus signal; multiplexed with SLCDC1_DAT12 through PC10
Preliminary—Subject to Change Without Notice
i.MX27 and i.MX27L Data Sheet, Rev. 1.2
General Purpose Timers (X6)
USB2.0
Function/Notes
Freescale Semiconductor