mcimx27- Freescale Semiconductor, Inc, mcimx27- Datasheet - Page 58

• Manufacturer Part Number: mcimx27-
• Description: Multimedia Applications Processor
• Manufacturer: Freescale Semiconductor, Inc

1
1
Signal Descriptions
3.6.2.2
The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. In addition, the FEC IPG clock frequency must exceed twice the
FEC_TX_CLK frequency.
Figure 18
3.6.2.3
Figure 19
58
M3
M4
M5
M6
M7
M8
FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.
ID
ID
FEC_TXD[3:0] (outputs)
FEC_TX_CLK (input)
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
FEC_TX_CLK pulse width high
FEC_TX_CLK pulse width low
shows the MII transmit signal timings, and
shows the MII asynchronous input timings, and
FEC_RX_CLK pulse width high
FEC_RX_CLK pulse width low
FEC_CRS, FEC_COL
MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER,
and FEC_TX_CLK)
MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL)
FEC_TX_EN
FEC_TX_ER
Table 25. MII Receive Signal Timing Parameters (continued)
Figure 19. MII Asynchronous Inputs Signal Timing Diagram
Table 26. MII Transmit Signal Timing Parameters
Figure 18. MII Transmit Signal Timing Diagram
Parameter
Preliminary—Subject to Change Without Notice
i.MX27 and i.MX27L Data Sheet, Rev. 1.2
Parameter
1
1
M5
M6
M7
Table 26
Table 27
M9
lists the timing parameters.
35%
35%
Min
lists the timing parameters.
M8
35%
35%
Min
—
Max
65%
65%
5
65%
65%
Max
20
—
FEC_RX_CLK period
FEC_RX_CLK period
Freescale Semiconductor
FEC_TX_CLK period
FEC_TX_CLK period
Unit
Unit
ns
ns