mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 68

• Manufacturer Part Number: mc9s12e256
• Description: Hcs12 Microcontrollers 16-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1)
1.4.37
PS0 is a general purpose input or output. When the Serial Communications Interface 0 (SCI0) receiver is
enabled the PS0 pin is configured as the receive pin RXD0 of SCI0. While in reset and immediately out
of reset the PS0 pin is configured as a high impedance input pin. Consult
Module (PIM9E256V1)”
about pin configurations.
1.4.38
PT[7:4] are general purpose input or output pins. When the Timer system 1 (TIM1) is enabled they can
also be configured as the TIM1 input capture or output compare pins IOC1[7-4]. While in reset and
immediately out of reset the PT[7:4] pins are configured as a high impedance input pins. Consult
Chapter 3, “Port Integration Module (PIM9E256V1)”
for information about pin configurations.
1.4.39
PT[3:0] are general purpose input or output pins. When the Timer system 0 (TIM0) is enabled they can
also be configured as the TIM0 input capture or output compare pins IOC0[7-4]. While in reset and
immediately out of reset the PT[3:0] pins are configured as a high impedance input pins. Consult
Chapter 3, “Port Integration Module (PIM9E256V1)”
for information about pin configurations.
1.4.40
PU[7:6] are general purpose input or output pins. While in reset and immediately out of reset the PU[7:6]
pins are configured as a high impedance input pins. Consult
(PIM9E256V1)”
version.
1.4.41
PU[5:4] are general purpose input or output pins. When the Pulse Width Modulator (PWM) is enabled the
PU[5:4] output pins, individually or as a pair, can be configured as PW1[5:4] outputs. While in reset and
immediately out of reset the PU[5:4] pins are configured as a high impedance input pins. Consult
Chapter 3, “Port Integration Module (PIM9E256V1)”
(PWM8B6CV1)”
version.
1.4.42
PU[3:0] are general purpose input or output pins. When the Timer system 2 (TIM2) is enabled they can
also be configured as the TIM2 input capture or output compare pins IOC2[7-4]. When the Pulse Width
Modulator (PWM) is enabled the PU[3:0] output pins, individually or as a pair, can be configured as
PW1[3:0] outputs. The MODRR register in the Port Integration Module determines if the TIM2 or PWM
68
PS0 / RXD0 — Port S I/O Pin 0
PT[7:4] / IOC1[7:4]— Port T I/O Pins [7:4]
PT[3:0] / IOC0[7:4]— Port T I/O Pins [3:0]
PU[7:6] — Port U I/O Pins [7:6]
PU[5:4] / PW1[5:4] — Port U I/O Pins [5:4]
PU[3:0] / IOC2[7:4]/PW1[3:0] — Port U I/O Pins [3:0]
for information about pin configurations. PU[7:6] are not available in the 80 pin package
for information about pin configurations. PU[5:4] are not available in the 80 pin package
and
Chapter 8, “Serial Communication Interface (SCIV4)”
MC9S12E256 Data Sheet, Rev. 1.08
and
and
and
Chapter 13, “Timer Module (TIM16B4CV1)”
Chapter 13, “Timer Module (TIM16B4CV1)”
Chapter 12, “Pulse-Width Modulator
Chapter 3, “Port Integration Module
Chapter 3, “Port Integration
Freescale Semiconductor
for information