mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 174

• Manufacturer Part Number: mc9s12e256
• Description: Hcs12 Microcontrollers 16-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 4 Clocks and Reset Generator (CRGV4)
4.3.2.6
This register controls CRG clock selection. Refer to
Read: anytime
Write: refer to each bit for individual write conditions
174
SYSWAI
ROAWAI
PLLSEL
PLLWAI
Reset
PSTP
CWAI
Field
7
6
5
4
3
2
W
R
PLLSEL
PLL Select Bit — Write anytime. Writing a 1 when LOCK = 0 and AUTO = 1, or TRACK = 0 and AUTO = 0 has
no effect. This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU
enters self-clock mode, stop mode or wait mode with PLLWAI bit set.
0 System clocks are derived from OSCCLK (Bus Clock = OSCCLK / 2).
1 System clocks are derived from PLLCLK (Bus Clock = PLLCLK / 2).
Pseudo-Stop Bit — Write: anytime — This bit controls the functionality of the oscillator during stop mode.
0 Oscillator is disabled in stop mode.
1 Oscillator continues to run in stop mode (pseudo-stop). The oscillator amplitude is reduced. Refer to oscillator
Note: Pseudo-stop allows for faster stop recovery and reduces the mechanical stress and aging of the resonator
Note: Lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any
System Clocks Stop in Wait Mode Bit — Write: anytime
0 In wait mode, the system clocks continue to run.
1 In wait mode, the system clocks stop.
Note: RTI and COP are not affected by SYSWAI bit.
Reduced Oscillator Amplitude in Wait Mode Bit — Write: anytime — Refer to
for availability of a reduced oscillator amplitude. If no such feature exists in the oscillator block then setting this
bit to 1 will not have any effect on power consumption.
0 Normal oscillator amplitude in wait mode.
1 Reduced oscillator amplitude in wait mode.
Note: Lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any
PLL Stops in Wait Mode Bit — Write: anytime — If PLLWAI is set, the CRGV4 will clear the PLLSEL bit before
entering wait mode. The PLLON bit remains set during wait mode but the PLL is powered down. Upon exiting
wait mode, the PLLSEL bit has to be set manually if PLL clock is required.
While the PLLWAI bit is set the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected
target frequency after exiting wait mode.
0 PLL keeps running in wait mode.
1 PLL stops in wait mode.
Core Stops in Wait Mode Bit — Write: anytime
0 Core clock keeps running in wait mode.
1 Core clock stops in wait mode.
CRG Clock Select Register (CLKSEL)
0
7
block description for availability of a reduced oscillator amplitude.
in case of frequent stop conditions at the expense of a slightly increased power consumption.
electro-magnetic susceptibility (EMS) tests.
electro-magnetic susceptibility (EMS) tests.
PSTP
0
6
Figure 4-9. CRG Clock Select Register (CLKSEL)
Table 4-4. CLKSEL Field Descriptions
SYSWAI
MC9S12E256 Data Sheet, Rev. 1.08
0
5
ROAWAI
0
4
Figure 4-17
Description
PLLWAI
3
0
for details on the effect of each bit.
CWAI
0
2
Chapter 5, “Oscillator (OSCV2)”
RTIWAI
Freescale Semiconductor
0
1
COPWAI
0
0