mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 213

• Manufacturer Part Number: mc9s12e256
• Description: Hcs12 Microcontrollers 16-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

6.3.2.3
This register controls power down, interrupt and external trigger. Writes to this register will abort current
conversion sequence but will not start a new sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
ETRIGLE
Reset
ETRIGP
ETRIGE
ADPU
AFFC
AWAI
Field
W
7
6
5
4
3
2
R
ADPU
ATD Control Register 2 (ATDCTL2)
0
7
ATD Power Down — This bit provides on/off control over the ATD10B16C block allowing reduced MCU power
consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time
period after ADPU bit is enabled.
0 Power down ATD
1 Normal ATD functionality
ATD Fast Flag Clear All
0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to
1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will
ATD Power Down in Wait Mode — When entering Wait Mode this bit provides on/off control over the
ATD10B16C block allowing reduced MCU power. Because analog electronic is turned off when powered down,
the ATD requires a recovery time period after exit from Wait mode.
0 ATD continues to run in Wait mode
1 Halt conversion and power down ATD during Wait mode
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 6-7
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See
details.
External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of
the ETRIG[3:0] inputs as described in
input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with
external events.
0 Disable external trigger
1 Enable external trigger
clear the associate CCF flag).
cause the associate CCF flag to clear automatically.
After exiting Wait mode with an interrupt conversion will resume. But due to the recovery time the result of
this conversion should be ignored.
= Unimplemented or Reserved
for details.
AFFC
0
6
Figure 6-5. ATD Control Register 2 (ATDCTL2)
Table 6-6. ATDCTL2 Field Descriptions
AWAI
MC9S12E256 Data Sheet, Rev. 1.08
0
5
Table
ETRIGLE
0
6-5. If external trigger source is one of the AD channels, the digital
4
Description
ETRIGP
Chapter 6 Analog-to-Digital Converter (ATD10B16CV4)
3
0
ETRIGE
0
2
ASCIE
0
1
Table 6-7
ASCIF
for
0
0
213