mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 331
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mc9s12e256
Manufacturer Part Number
mc9s12e256
Description
Hcs12 Microcontrollers 16-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12E256.pdf
(602 pages)
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11.3.2.5
Read and write anytime.
11.3.2.6
Read anytime. This register cannot be modified after the WP bit is set.
Freescale Semiconductor
FMODE[3:0]
Module Base + 0x0004
Module Base + 0x0005
FPINE[2:0]
7, 5, 3, 1
6, 4, 2, 0
6, 4, 2, 0
FIE[3:0]
Reset
Reset
Field
Field
W
W
R
R
FMODE3
Fault x Pin Clearing Mode — This bit selects automatic or manual clearing of FAULTx pin faults. See
Section 11.4.8.2, “Automatic Fault Clearing”
0 Manual fault clearing of FAULTx pin faults.
1 Automatic fault clearing of FAULTx pin faults.
where x is 0, 1, 2, and 3.
Fault x Pin Interrupt Enable — This bit enables CPU interrupt requests to be generated by the FAULTx pin. The
fault protection circuit is independent of the FIEx bit and is active when FPINEx is set. If a fault is detected, the
PWM pins are disabled according to the PMF Disable Mapping registers.
0 Fault x CPU interrupt requests disabled.
1 Fault x CPU interrupt requests enabled.
where x is 0, 1, 2 and 3.
Fault x Pin Enable — Where x is 0, 1, 2 and 3.
0 FAULTx pin is disabled for fault protection.
1 FAULTx pin is enabled for fault protection.
PMF Fault Control Register (PMFFCTL)
PMF Fault Pin Enable Register (PMFFPIN)
0
0
0
7
7
= Unimplemented or Reserved
FPINE3
FIE3
Figure 11-9. PMF Fault Pin Enable Register (PMFFPIN)
0
0
6
6
Figure 11-8. PMF Fault Control Register (PMFFCTL))
Table 11-6. PMFFCTL Field Descriptions
Table 11-7. PMFFPIN Field Descriptions
FMODE2
MC9S12E256 Data Sheet, Rev. 1.08
0
0
0
5
5
FPINE2
Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
FIE2
and
0
0
4
4
Section 11.4.8.3, “Manual Fault Clearing”
Description
Description
FMODE1
3
0
3
0
0
FPINE1
FIE1
0
0
2
2
FMODE0
0
0
0
1
1
for more details.
FPINE0
FIE0
0
0
0
0
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