mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 462

• Manufacturer Part Number: mc9s12e256
• Description: Hcs12 Microcontrollers 16-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 15 Background Debug Module (BDMV4)
Figure 15-11
instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the
address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed
(free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the
BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved.
After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the
form of a word and the host needs to determine which is the appropriate byte based on whether the address
was odd or even.
Differently from the normal bit transfer (where the host initiates the transmission), the serial interface
ACK handshake pulse is initiated by the target MCU by issuing a falling edge in the BKGD pin. The
hardware handshake protocol in
the host should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD
pin.
The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not
acknowledge by an ACK pulse, the host needs to abort the pending command first in order to be able to
issue a new BDM command. When the CPU enters WAIT or STOP while the host issues a command that
requires CPU execution (e.g., WRITE_BYTE), the target discards the incoming command due to the
WAIT or STOP being detected. Therefore, the command is not acknowledged by the target, which means
that the ACK pulse will not be issued in this case. After a certain time the host should decide to abort the
ACK sequence in order to be free to issue a new command. Therefore, the protocol should provide a
mechanism in which a command, and therefore a pending ACK, could be aborted.
462
BKGD PIN
shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE
READ_BYTE
The only place the BKGD pin can have an electrical conflict is when one
side is driving low and the other side is issuing a speedup pulse (high). Other
“highs” are pulled rather than driven. However, at low rates the time of the
speedup pulse can become lengthy and so the potential conflict time
becomes longer as well.
Differently from a regular BDM command, the ACK pulse does not provide
a time out. This means that in the case of a WAIT or STOP instruction being
executed, the ACK would be prevented from being issued. If not aborted,
the ACK would remain pending indefinitely. See the handshake abort
procedure described in
Procedure.”
HOST
Figure 15-11. Handshake Protocol at Command Level
BYTE ADDRESS
TARGET
Figure 15-10
THE COMMAND
BDM DECODES
MC9S12E256 Data Sheet, Rev. 1.08
Section 15.4.8, “Hardware Handshake Abort
specifies the timing when the BKGD pin is being driven, so
NOTE
NOTE
BDM EXECUTES THE
READ_BYTE COMMAND
TARGET
BDM ISSUES THE
ACK PULSE (OUT OF SCALE)
(2) BYTES ARE
RETRIEVED
HOST
Freescale Semiconductor
HOST
COMMAND
NEW BDM
TARGET