mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 399

no-image

mc9s12e256

Manufacturer Part Number
mc9s12e256
Description
Hcs12 Microcontrollers 16-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc9s12e256CFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12e256CPVE
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
mc9s12e256CPVE
Manufacturer:
FREESCA
Quantity:
300
Part Number:
mc9s12e256CPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12e256MFUE
Manufacturer:
FREESCAL
Quantity:
329
Part Number:
mc9s12e256MFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12e256MPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12e256VFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 12 Pulse-Width Modulator (PWM8B6CV1)
12.4
Functional Description
12.4.1
PWM Clock Select
There are four available clocks called clock A, clock B, clock SA (scaled A), and clock SB (scaled B).
These four clocks are based on the bus clock.
Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA
uses clock A as an input and divides it further with a reloadable counter. Similarly, clock SB uses clock B
as an input and divides it further with a reloadable counter. The rates available for clock SA are software
selectable to be clock A divided by 2, 4, 6, 8, ..., or 512 in increments of divide by 2. Similar rates are
available for clock SB. Each PWM channel has the capability of selecting one of two clocks, either the
pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB).
The block diagram in
Figure 12-34
shows the four different clocks and how the scaled clocks are created.
12.4.1.1
Prescale
The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze
mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze
mode the input clock to the prescaler is disabled. This is useful for emulation in order to freeze the PWM.
The input clock can also be disabled when all six PWM channels are disabled (PWME5–PWME0 = 0)
This is useful for reducing power by disabling the prescale counter.
Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock A
and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. The value
selected for clock A is determined by the PCKA2, PCKA1, and PCKA0 bits in the PWMPRCLK register.
The value selected for clock B is determined by the PCKB2, PCKB1, and PCKB0 bits also in the
PWMPRCLK register.
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
399

Related parts for mc9s12e256