mc9s12e256 Freescale Semiconductor, Inc, mc9s12e256 Datasheet - Page 440

• Manufacturer Part Number: mc9s12e256
• Description: Hcs12 Microcontrollers 16-bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Chapter 14 Dual Output Voltage Regulator (VREG3V3V2)
14.2.3
Signals V
signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R
ceramic).
In shutdown mode an external supply at V
14.2.4
Signals V
and oscillator. These signals are connected to device pins to allow external decoupling capacitors (100
nF...220 nF, X7R ceramic).
In shutdown mode an external supply at V
14.2.5
This optional signal is used to shutdown VREG. In that case V
provided externally. shutdown mode is entered with V
either in full-performance mode or in reduced-power mode.
For the connectivity of V
14.3
This subsection provides a detailed description of all registers accessible in VREG.
14.3.1
Figure 14-2
440
DD
DDPLL
Memory Map and Register Definition
Address
0x0000
Offset
V
V
V
Module Memory Map
provides an overview of all used registers.
/V
DD
DDPLL
REGEN
SS
Switching from FPM or RPM to shutdown of VREG and vice versa is not
supported while the MCU is powered.
/V
, V
are the primary outputs of VREG that provide the power supply for the core logic. These
SSPLL
VREG Control Register (VREGCTRL)
SS
, V
— Optional Regulator Enable
REGEN
— Regulator Output1 (Core Logic)
are the secondary outputs of VREG that provide the power supply for the PLL
SSPLL
see
— Regulator Output2 (PLL)
Chapter 1, “MC9S12E256 Device Overview
MC9S12E256 Data Sheet, Rev. 1.08
Table 14-2. VREG Memory Map
DD
DDPLL
/V
SS
/V
NOTE
can replace the voltage regulator.
Use
SSPLL
REGEN
can replace the voltage regulator.
being low. If V
DD
/V
SS
and V
REGEN
DDPLL
(MC9S12E256DGV1)”.
/V
is high, the VREG is
Freescale Semiconductor
SSPLL
Access
R/W
must be