hyb18m1g16 Qimonda, hyb18m1g16 Datasheet - Page 56

• Manufacturer Part Number: hyb18m1g16
• Description: Drams For Mobile Applications 1-gbit X16 Ddr Mobile-ram Rohs Compliant
• Manufacturer: Qimonda

1) All parameters assume proper device initialization.
2) The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals
3) All AC timing characteristics assume an input slew rate of 1.0 V/ns.
4) The output timing reference level is
5) Parameters
6) Min (
7) t
t
transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data ball skew
and output pattern effects, and p-channel to n-channel variation of the output drivers.
8) The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes.
9) DQ, DM and DQS input slew rate is measured between
10) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions
11) Input slew rate ≥ 1.0 V/ns.
12) Input slew rate ≥ 0.5V/ns and < 1.0 V/ns.
13) These parameters guarantee device timing. They are verified by device characterization but are not subject to production test.
14) The transition time for address and command inputs is measured between
15) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
16)
17) t
given cycle.
18) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
Rev.1.0, 2007-03
10242006-Y557-TZXW
QHS
Parameter
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period
AUTO REFRESH to ACTIVE/AUTO REFRESH
command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B delay
WRITE recovery time
Auto precharge write recovery + precharge time
Internal write to Read command delay
Self refresh exit to next valid command delay
Exit power down delay
CKE minimum high or low time
Refresh period
Average periodic refresh interval (8192 rows)
QH
other than CK/CK is V
a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half
drive strength with a nominal load of 10pF parameters
are not subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation
is suggested.
be greater than the minimum specification limits for
through the DC region must be monotonic.
t
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on t
DQSQ
HZ
accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one
= t
and
t
HP
CL
consists of data ball skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any
,
t
- t
LZ
t
CH
QHS
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
t
AC
, where t
and
t
DQSCK
DDQ
HP
/2.
are specified for full drive strength and a reference load (see
= minimum half clock period for any given cycle and is defined by clock high or clock low ( t
V
DDQ
/2.
DQSS
.
t
CL
t
and
AC
V
ILD(DC)
and
t
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CH
RAS
RC
RFC
RCD
RP
RRD
WR
DAL
WTR
XSR
XP
CKE
REF
REFI
).
t
DQSCK
and
56
V
are expected to be in the same range. However, these parameters
IHD(AC)
42
60
72
18
18
12
15
1
120
t
2
–
–
CK
min.
+
V
(rising) or
t
IH
IS
and
- 6
70,000
–
–
–
–
–
–
–
–
–
–
64
7.8
V
max.
IL
.
V
Figure 40
IHD(DC)
45
65
75
22.5
22.5
15
15
1
120
t
2
–
–
CK
and
min.
+
). This circuit is not intended to be either
t
V
IS
- 7.5
ILD(AC)
70,000
–
–
–
–
–
–
–
–
–
–
64
7.8
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
max.
(falling).
Unit Note
ns
ns
ns
ns
ns
ns
ns
t
t
ns
ns
t
ms
µs
CK
CK
CK
1)2)3)21)
1)2)3)21)
1)2)3)21)
1)2)3)21)
1)2)3)21)
1)2)3)21)
1)2)3)21)
1)2)3)22)
1)2)3)
1)2)3)21)
1)2)3)
1)2)3)
1)2)3)
1)2)3)23)
Data Sheet
CL
, t
CH
).