hyb18m1g16 Qimonda, hyb18m1g16 Datasheet - Page 27

• Manufacturer Part Number: hyb18m1g16
• Description: Drams For Mobile Applications 1-gbit X16 Ddr Mobile-ram Rohs Compliant
• Manufacturer: Qimonda

Full-speed random READ accesses (Burst Length = 2, 4, 8 or 16) within a page (or pages) can be performed as shown in
Figure
Note: This timing diagram is only applicable for the consecutive READ from the same die.
2.4.5.1
Data from any READ burst may be truncated using the BURST TERMINATE command (see
Precharge was not activated. The BURST TERMINATE latency is equal to the CAS latency, i.e. the BURST TERMINATE
command should be issued x clock cycles after the READ command, where x equals the number of desired data element pairs.
This is shown in
Rev.1.0, 2007-03
10242006-Y557-TZXW
Command
Address
DO n, etc. = Data Out from column n, etc.
n', x', etc. = Data Out elements, according to the programmed burst order
BA, Col n = Bank A, Column n
Burst Length = 2, 4, 8 or 16 in cases shown (if burst of 4, 8 or 16, the burst is interrupted)
Reads are to active rows in any banks
17.
DQS
DQS
DQ
DQ
CK
CK
Figure
BA,Col n
READ
READ Burst Termination
18.
CL=2
BA,Col x
READ
CL=3
DO n
BA,Col b
READ
27
DO n'
DO n
DO x
BA,Col g
READ
DO n'
DO x'
DO b
DO x
NOP
Random READ Accesses
Figure
DO b'
DO x'
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
21), provided that Auto
DO g
DO b
FIGURE 17
= Don't Care
NOP
Data Sheet
DO g'
DO b'