hyb18m1g16 Qimonda, hyb18m1g16 Datasheet - Page 14

• Manufacturer Part Number: hyb18m1g16
• Description: Drams For Mobile Applications 1-gbit X16 Ddr Mobile-ram Rohs Compliant
• Manufacturer: Qimonda

2.2.2
The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh
(PASR), the Temperature Compensated Self Refresh (TCSR) and the drive strength selection for the DQs. The Extended
Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored
information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements result in unspecified operation. Address bits A0 -
zero. Bits A3 and A4 are “don’t care” (see below).
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Extended Mode Register Definition (BA[1:0] = 10
2.2.2.1
Partial Array Self Refresh is a power-saving feature specific to DDR Mobile-RAMs. With PASR, self refresh may be restricted
to variable portions of the total array. The selection comprises all four banks (default), two banks, one bank, half of one bank,
and a quarter of one bank. Data written to the non activated memory sections will get lost after a period defined by
Table
Rev.1.0, 2007-03
10242006-Y557-TZXW
Field
DS
TCSR
PASR
A2 specify the Partial Array Self Refresh (PASR) and bits A5 - A6 the Drive Strength, while bits A7 - A12 shall be written to
14).
Bits
[6:5]
[4:3]
[2:0]
Type
w
w
w
Extended Mode Register
Partial Array Self Refresh (PASR)
Description
Selectable Drive Strength
00
01
10
Note: All other bit combinations are RESERVED.
Temperature Compensated Self Refresh
XX
Partial Array Self Refresh
000
001
010
101
110
Note: All other bit combinations are RESERVED.
B
B
B
B
B
B
B
B
B
DS Full Drive Strength
DS Half Drive Strength
DS Quarter Drive Strength
TCSR Superseded by on-chip temperature sensor (see text)
PASR all banks
PASR half array (BA1 = 0)
PASR quarter array (BA1 = BA0 = 0)
PASR 1/8 array (BA1 = BA0 = RA12 = 0)
PASR 1/16 array (BA1 = BA0 = RA12 = RA11 = 0)
B
)
14
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
Data Sheet
t
REF
(cf.