hyb18m1g16 Qimonda, hyb18m1g16 Datasheet - Page 24

• Manufacturer Part Number: hyb18m1g16
• Description: Drams For Mobile Applications 1-gbit X16 Ddr Mobile-ram Rohs Compliant
• Manufacturer: Qimonda

1) The output timing reference level is V
2) Parameters
3)
4) t
given cycle.
5)
6) These parameters account for the number of clock cycles and depend on the operating frequency, as follows:
During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency
after the READ command.
The diagrams in
RAM along with output data. The initial low state on DQS is known as the read preamble; the low state coincident with the last
data-out element is known as the read postamble.
Upon completion of a burst, assuming no other READ commands have been initiated, the DQs will go High-Z.
Rev.1.0, 2007-03
10242006-Y557-TZXW
Parameter
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQSQ
precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half drive
strength with a nominal load of 10pF parameters
subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation is
suggested.
t
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
t
for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data ball skew and output pattern effects, and p-channel to
n-channel variation of the output drivers.
no. of clock cycles = specified delay / clock period; round to the next higher integer.
HZ
QH
Command
Address
and
DO n = Data Out from column n
BA, Col n = Bank A, Column n
Burst Length = 4; 3 subsequent elements of Data Out appear in the programmed order following DO n
=
consists of data ball skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any
t
HP
DQS
DQS
t
LZ
DQ
DQ
-
CK
CK
t
QHS
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
t
AC
, where
Figure 14
and
BA,Col n
READ
t
QH
t
HP
are specified for full drive strength and a reference load of 20pF. This reference load is not intended to be either a
= minimum half clock period for any given cycle and is defined by clock high or clock low (
show general timing for each supported CAS latency setting. DQS is driven by the DDR Mobile-
CL=2
DDQ
NOP
/2.
t
AC
and
CL=3
DO n
t
QH
NOP
are expected to be in the same range. However, these parameters are not
t
t
Symbol
RCD
RP
24
18
18
min.
DO n
NOP
- 6
–
–
max.
22.5
22.5
NOP
min.
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
- 7.5
–
–
max.
t
CL
FIGURE 14
= Don't Care
NOP
,
t
CH
READ Burst
).
Unit
ns
ns
Data Sheet
t
QHS
accounts
Note
6)
6)