mt29f1gxxabb Micron Semiconductor Products, mt29f1gxxabb Datasheet - Page 31

• Manufacturer Part Number: mt29f1gxxabb
• Description: 1gb X8, X16 Nand Flash Memory
• Manufacturer: Micron Semiconductor Products

Figure 20:
PROGRAM PAGE CACHE MODE 80h-15h
PDF: 09005aef81dc05df / Source: 09005aef821d5f08
1gb_nand_m48a__2.fm - Rev. E 1/08 EN
R/B#
I/Ox
80h
RANDOM DATA INPUT
Address
Cache programming is actually a buffered programming mode of the standard page pro-
gramming command. Programming is started by loading the SERIAL DATA INPUT (80h)
command to the command register, followed by 4 cycles of address, and a full or partial
page of data. The data is initially copied into the cache register, and the CACHE WRITE
(15h) command is then latched to the command register. Data is transferred from the
cache register to the data register on the rising edge of WE#. R/B# goes LOW during this
transfer time. After the data has been copied into the data register and R/B# returns to
HIGH, memory array programming begins.
When R/B# returns to HIGH, new data can be written to the cache register by issuing
another PROGRAM PAGE CACHE MODE command sequence. The time that R/B# stays
LOW will be controlled by the actual programming time. The first time through equals
the time it takes to transfer the cache register contents to the data register. On the sec-
ond and subsequent programming passes, transfer from the cache register to the data
register is held off until current data register content has been programmed into the
array.
The PROGRAM PAGE CACHE MODE command can cross block address boundaries; it
must not cross die address boundaries. RANDOM DATA INPUT (85h) commands are
permitted with PROGRAM PAGE CACHE MODE operations.
Bit 6 (cache R/B#) of the status register can be read by issuing the READ STATUS (70h)
command to determine when the cache register is ready to accept new data. R/B#
always follows bit 6.
Bit 5 (R/B#) of the status register can be polled to determine when the actual program-
ming of the array is complete for the current programming cycle.
If R/B# is used to determine programming completion, the last page of the program
sequence must use the PROGRAM PAGE (10h) command instead of the CACHE PRO-
GRAM (15h) command. If the CACHE PROGRAM (15h) command is used every time,
including the last page of the programming sequence, status register bit 5 must be used
to determine when programming is complete.
Bit 1 of the status register returns the pass/fail for the previous page when bit 6 of the
status register is a “1” (ready state). The pass/fail status of the current PROGRAM opera-
tion is returned with bit 0 of the status register when bit 5 of the status register is a “1”
(ready state) (see Figure 21 on page 32).
D
IN
85h
Address (2 cycles)
31
D
IN
10h
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x8, x16 NAND Flash Memory
t PROG
70h
Command Definitions
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