mt29f1gxxabb Micron Semiconductor Products, mt29f1gxxabb Datasheet - Page 16

• Manufacturer Part Number: mt29f1gxxabb
• Description: 1gb X8, X16 Nand Flash Memory
• Manufacturer: Micron Semiconductor Products

Bus Operation
Control Signals
Commands
Address Input
PDF: 09005aef81dc05df / Source: 09005aef821d5f08
1gb_nand_m48a__2.fm - Rev. E 1/08 EN
The bus on the MT29F1Gxx devices is multiplexed. Data I/O, addresses and commands
all share the same balls. I/O[15:8] are used only for data in the x16 configuration.
Addresses and commands are always supplied on I/O[7:0].
The command sequence normally consists of a COMMAND LATCH cycle, ADDRESS
LATCH cycle and a DATA cycle—either READ or WRITE.
CE#, WE#, RE#, CLE, ALE, LOCK, and WP control NAND Flash READ and WRITE opera-
tions.
CE# is used to enable the device. When CE# is LOW and the device is not in the BUSY
state, the NAND Flash memory will accept command, data, and address information.
When the device is not performing an operation, CE# is typically driven HIGH and the
device enters standby mode. The memory will enter standby if CE# goes HIGH while
data is being transferred and the device is not busy. This helps reduce power consumption
(see Figure 57 on page 64).
The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-
chronous memory bus as other Flash or SRAM devices. Other devices on the memory
bus can then be accessed while the NAND Flash is busy with internal operations. This
capability is important for designs that require multiple NAND Flash devices on the
same bus. One device can be programmed while another is being read.
A HIGH CLE signal indicates that a COMMAND cycle is taking place. A HIGH ALE signal
signifies that an ADDRESS INPUT cycle is occurring.
Commands are written to the command register on the rising edge of WE# when all of
these conditions are met:
• CE# and ALE are LOW
• CLE is HIGH
• the device is not busy
The READ STATUS and RESET commands are different because they can be written to
the device while it is busy. Commands are transferred to the command register on the
rising edge of WE# (see Figure 26 on page 37).
Commands are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be
written with zeros when issuing a command.
Addresses are written to the address register on the rising edge of WE# when all of these
conditions are met:
• CE# and CLE are LOW
• ALE is HIGH
Addresses are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be
written with zeros when issuing an address.
Generally, all 4 address cycles are written to the device. An exception is the BLOCK
ERASE command, which requires only 2 address cycles (see “BLOCK ERASE Operation”
on page 33 for details).
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x8, x16 NAND Flash Memory
©2006 Micron Technology, Inc. All rights reserved.
Bus Operation