sak-c868p-1rr Infineon Technologies Corporation, sak-c868p-1rr Datasheet - Page 182

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sak-c868p-1rr

Manufacturer Part Number
sak-c868p-1rr
Description
8 - Bit Cmos Microcontroller
Manufacturer
Infineon Technologies Corporation
Datasheet
SCUWDT
SCU/Watchdog Control Register
Field
WDTRE
WDTRS
WDTDIS
WDTEOI
WDTR
PLLR
-
User’s Manual
7
-
r
PLLR
rwh
6
Bits
0
1
2
3
4
6
7,5
5
-
r
Typ Description
rw
rw
rw
rw
rwh WDT Reset Indication Bit.
rwh PLL Reset Indication Bit.
r
WDT Refresh Enable.
Active high. Set to enable a refresh of the watchdog
timer. Must be set before WDTRS.
WDT Refresh Start.
Active high. Set to start refresh operation on the
watchdog timer. Must be set after WDTRE.
WDT Disable.
Active high. Set by software and cleared by general
reset. Writing to this bit has no effect if WDTEOI is
set.
WDT End of Initialization.
Active high. Set by software and cleared by general
reset.
Active high. Set by hardware when a watchdog timer
reset occurs. Cleared by reset or WDT_RFSH or
software.
Active high. Set by hardware when PLL reset occurs.
Cleared by reset or software.
reserved;
returns ’0’ if read; should be written with ’0’;
WDTR
rwh
4
6-4
WDTEOI
rw
3
WDTDIS
rw
2
Fail Save Mechanism
WDTRS
[Reset value: 00
rw
1
V 1.0, 2003-01
WDTRE
rw
C868
0
H
]

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