sak-c868p-1rr Infineon Technologies Corporation, sak-c868p-1rr Datasheet - Page 168

• Manufacturer Part Number: sak-c868p-1rr
• Description: 8 - Bit Cmos Microcontroller
• Manufacturer: Infineon Technologies Corporation

The time required for a reset operation must be at least tbd - tbd usec. The same
considerations apply if the reset signal is generated externally
case it must be assured that the logic at ALE/BSL and TxD are latched properly.
Figure 5-1
A correct reset leaves the processor in a defined state. The program execution starts at
location 0000
defaulted to FF
The contents of the internal RAM and XRAM of the C868 are not affected by a reset.
After power-up the contents are undefined, while it remains unchanged during a reset if
the power supply is not turned off.
5.2
Figure 5-2
For the C868, the device enter into default reset state once RESET has gone low with
all I/O ports set to input or high impedance. The internal reset is released only after the
PLL has locked. In
RESET pin had gone high, the I/O ports 1 and 3 remain as input. In
detection for continuous PLL lock is done before internal reset is released. The 4096
cycles of continuous lock detection ensures that a reset due to PLL unlock will not
happen during the transient period after the PLL started functioning. After continuous
PLL lock is detected, the C868 starts
User’s Manual
V
DDP
a)
RESET
Internal Reset after Power-On
shows the power-on sequence.
C868
H
Reset Circuitries
. After reset is internally accomplished the port latches of ports 1 and 3
H
, and they are set to input.
(Figure
5-2,II) the internal reset remains active even after the
&
Reset, Brownout and System Clock Operation
operation.(Figure
b)
RESET
C868
5-2
5-2,IV)
(Figure 5-1
V
DDP
(Figure
V 1.0, 2003-01
c)
RESET
b). In each
C868
5-2,III),
C868