sak-c868p-1rr Infineon Technologies Corporation, sak-c868p-1rr Datasheet - Page 172

• Manufacturer Part Number: sak-c868p-1rr
• Description: 8 - Bit Cmos Microcontroller
• Manufacturer: Infineon Technologies Corporation

5.5.1
The frequency range for f
5.5.2
The K-Divider is a software controlled divider. The bit field KDIV is provided in register
CMCON. Software can write to this field in order to change the PLL frequency f
default KDIV value is 4.
division factor.
The divider is designed such that a synchronous switching of the clock is performed
without spurious or shortened clock pulses when software changes the divider factor
KDIV. However, special attention has to be paid concerning the effect of such a clock
change to the various modules in the system.
5.5.3
This section gives the formulas for the determination of the PLL clock frequency. In PLL
operation, the PLL clock is derived from the VCO frequency f
f
The PLL clock frequency f
CMCON.KDIV determines the clock scale factor K. The VCO output frequency is
determined by:
and the resulting PLL clock is determined by:
Since stable operation of the VCO is only guaranteed if f
defined frequency range for the VCO (see
is also confined to certain ranges.
User’s Manual
VCO
is generated from the external clock multiplied by 15.
VCO Frequency Ranges
K-Divider
Determining the PLL Clock Frequency
100 MHz
VCO
Table 5-2
PLL
can be made proportional to the ratio 15 / K, where bit field
f
is:
PLL
=
Table 5-1
f
f
lists the possible values for KDIV and the resulting
f
VCO
VCO
VCO
Reset, Brownout and System Clock Operation
/ K =
= 15
5-6
Equation
160 MHz
list the range.
15
K
f
OSC
f
[5-1]), the external frequency f
OSC
VCO
VCO
divided by the K-factor.
remains inside of the
V 1.0, 2003-01
PLL
C868
. The
[5-1]
[5.2]
[5.3]
OSC