pga370 ETC-unknow, pga370 Datasheet - Page 92

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

Pentium
7.2
92
Table 42. Signal Description (Sheet 8 of 8)
Table 43. Output Signals
Table 44. Input Signals (Sheet 1 of 2)
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
VID[3:0]
V
V
V
V
V
Signal Summaries
Table 43
CORE DET
CC 1.5
CC 2.5
REF
CC CMOS
Name
A20M#
BPRI#
Name
BCLK
BR1#
THERMTRIP#
CPUPRES#
EDGCTRL
V
VID[3:0]
FERR#
PRDY#
CORE DET
IERR#
Name
through
Type
Active Level
O
O
O
I
I
I
Table 46
High
Low
Low
Low
The VID[3:0] (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to V
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on processors. See
pins. The power supply must supply the voltage that is requested by these pins, or
disable itself.
The V
2.0 V V
processor.
The V
interfacing to the processor. The Pentium III processor reroutes the 1.5 V input to
the V
used to supply V
The V
interfacing to processors which require 2.5 V termination on the CMOS signals. This
signal is not used by the Pentium III processor.
The VccCMOS pin provides the CMOS voltage for use by the platform and is used
for terminating CMOS signals that interface to the processor.
The V
V
logical 1.
TT
. V
list attributes of the processor output, input, and I/O signals.
CC CMOS
CORE DET
CC 1.5
CC 2.5
REF
Active Level
REF
CC CORE
input pins supply the AGTL+ reference voltage, which is typically 2/3 of
SS
is used by the AGTL+ receivers to determine if a signal is a logical 0 or a
Low
Low
Low
Low
Low
N/A
N/A
N/A
Asynch
V input pin provides the termination voltage for CMOS signals
V input pin provides the termination voltage for CMOS signals
Clock
BCLK
BCLK
output via the package. The supply for V
on the processor. The combination of opens and shorts defines the
—
pin indicate the type of processor core present. This pin will float for
based processor and will be shorted to V
TT .
System Bus Clock
Signal Group
AGTL+ Input
AGTL+ Input
CMOS Input
Description
Asynch
Asynch
Asynch
Asynch
Asynch
Asynch
Asynch
Clock
BCLK
Table 2
CC 1.5
SS
V must be the same one
for definitions of these
for the Pentium III
AGTL+ Output
Signal Group
CMOS Output
CMOS Output
CMOS Output
Power/Other
Power/Other
Power/Other
Power/Other
Qualified
Always
Always
Always
Always
Datasheet
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