pga370 ETC-unknow, pga370 Datasheet - Page 87

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

Datasheet
Table 42. Signal Description (Sheet 3 of 8)
BR0#
BR1#
BSEL[1:0]
CLKREF
Name
Type
Pentium
I/O
I/O
I
I
The BR0# and BR1# (Bus Request) pins drive the BREQ[1:0]# signals in the
system. The BREQ[1:0]# signals are interconnected in a rotating manner to
individual processor pins. The table below gives the rotating interconnect between
the processor and bus signals.
These signals are used to select the system bus frequency. A BSEL[1:0] = “01”
selects a 100 MHz system bus frequency and a BSEL[1:0] = “11” selects a 133 MHz
system bus frequency. The frequency is determined by the processor(s), chipset,
and frequency synthesizer capabilities. All system bus agents must operate at the
same frequency. The Pentium III processor for the PGA370 socket operates at
100 MHz and 133 MHz system bus frequencies. Individual processors will only
operate at their specified front side bus (FSB) frequency. Either 100 MHz or
133 MHz, not both.
On motherboards which support operation at either 66 MHz or 100 MHz, a
BSEL[1:0] = “x0” will select a 66 Mhz system bus frequency. 66 MHz operation is
not support by the Pentium III processor for the PGA370 socket; therefore, BSEL0 is
ignored.
These signals must be pulled up to 2.5 V or 3.3V with 1 K
as a frequency selection signal to the clock driver/synthesizer. If the system
motherboard is not capable of operating at 133 MHz, it should ground the BSEL1
signal and generate a 100 MHz system bus frequency. See
implementation examples.
The CLKREF input is a filtered 1.25 V supply voltage for the processor PLL. A
voltage divider and decoupling solution is provided by the motherboard. See the
design guide for implementation details.
BR0# (I/O) and BR1# Signals Rotating Interconnect
During power-up configuration, the central agent must assert the BR0# bus signal.
All symmetric agents sample their BR[1:0]# pins on active-to-inactive transition of
RESET#. The pin on which the agent samples an active level determines its
symmetric agent ID. All agents then configure their pins to match the appropriate
bus signal protocol, as shown below.
BR[1:0]# Signal Agent IDs
®
Pin Sampled Active in RESET#
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Bus Signal
BREQ0#
BREQ1#
BR0#
BR1#
Agent 0 Pins
BR0#
BR1#
Description
Agent 1 Pins
Agent ID
BR1#
BR0#
0
3
resistors and provided
Section 2.8.2
for
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