pga370 ETC-unknow, pga370 Datasheet - Page 38

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

Pentium
38
Table 15. System Bus Timing Specifications (Differential Clock)
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
10.This specification applies to Pentium III processors operating at a system bus frequency of 100 MHz.
10.Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
12.BCLK/BCLK# must rise/fall monotonically between Vil and Vih.
11. This specification applies to Pentium III processors operating at a system bus frequency of 133 MHz
11. AC parameters are measured at the processor pins.
3. Not 100% tested. Specified by design characterization as a clock driver requirement.
4. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the appropriate clock synthesizer/
6. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
7. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
8. BCLK Rise time is measure between 0.5 V–2.0 V. BCLK fall time is measured between 2.0 V–0.5 V.
9. BCLK high time is measured as the period of time above 2.0 V. BCLK low time is measured as the period of
1. Measurement taken from differential waveform, defined as BCLK - BCLK#.
2. Period is defined from one rising 0 V-crossing to the next.
3. Measurement taken from differential waveform, voltage range from -0.35 V to +0.35 V.
4. Measurement taken from common mode waveform, measure rise/fall time from 0.41 V to 0.86 V. Rise/fall
5. Period difference measured around 0 V-crossings; measurement taken from differential waveform.
6. The rising and falling edge ringback voltage specified is the minimum (rising) or them maximum (falling)
7. Measured in absolute voltage, i.e. single-ended measurement. Includes every cross point for both rise and
8. Input high or input low voltage range measured in absolute voltage, i.e. single-ended measurement.
9. The internal Core clock frequency is derived from the processor system bus clock. The system bus clock to
Clock Period—Average
Instantaneous Minimum Clock Period
CLK Differential Rise Time
CLK Differential Fall Time
Waveform Symmetry
Differential Cycle to Cycle Jitter
Differential Duty Cycle
Rising Edge Ring Back
Falling Edge Ring Back
Cross Point at 1V
Input High Voltage
Input Low Voltage
core clock ratio is determined during initialization. Individual processors will only operate at their specified
system bus frequency, either 100 MHz or 133 MHz, not both.
driver specification for details.
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor pin. The jitter present
must be accounted for as a component of BCLK timing skew between devices.
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer. See the appropriate clock synthesizer/driver specification for details
time below 0.5 V.
time matching is defined as “the instantaneous difference between maximum BCLK rise (fall) and minimum
BCLK# fall (rise) time, or minimum BCLK rise (fall) and maximum BCLK# fall (rise) time. “This parameter is
designed to guard waveform symmetry.
voltage, the differential waveform can go after passing Vih_diff (rising) or Vil_diff (falling)
fall of BCLK.
core clock ratio is determined during initialization. Individual processors will only operate at their specified
system bus frequency 133 MHz. Table 16 shows supported ratios for each processor
used that is designed to meet the period stability specification into a test load of 10 pF to 20 pF. The jitter
must be accounted for as a component of BCLK timing skew between devices.
Parameter
7.30
45%
0.35
0.92
–0.2
0.51
Min
175
175
7.5
133 MHz
–0.35
55%
1.45
0.35
Max
0.76
550
550
325
200
7.7
45%
10.0
0.35
0.51
0.92
–0.2
Min
175
175
9.8
100 MHz
1, 11, 12
–0.35
Max
10.2
55%
0.76
1.45
0.35
467
467
325
200
Units
ns
ns
ps
ps
ps
ps
V
V
V
V
V
2, 9, 10
2, 9, 10
Notes
Datasheet
1, 3
1, 3
1, 5
1, 6
1, 6
4
1
7
8
8