pga370 ETC-unknow, pga370 Datasheet - Page 14

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pga370

Manufacturer Part Number
pga370
Description
Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
Manufacturer
ETC-unknow
Datasheet
Pentium
2.2
14
Figure 2. AGTL+/AGTL Bus Topology in a Uniprocessor Configuration
Figure 3. AGTL+/AGTL Bus Topology in a Dual-Processor Configuration
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
system with a heavily loaded AGTL+ bus, especially for systems using a single set of termination
resistors (i.e., those on the processor die). Such designs will not match the solution space allowed
for by installation of termination resistors on the baseboard.
Clock Control and Low Power States
Processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on each
particular state. See
Figure 4
Processor
for a visual representation of the processor low-power states.
Processor
Chipset
Chipset
Processor
Datasheet

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