pga370 ETC-unknow, pga370 Datasheet - Page 24

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

Pentium
2.8.1
24
Table 4.
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
System Bus Signal Groups (AGTL)
NOTES:
Asynchronous vs. Synchronous for System Bus Signals
All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals
can be applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK.
10.For differential clock systems, the CLKREF pin becomes BCLK#.
12. 1.25 V signal for Differential clock application and 2.5 V for Single-ended clock application.
13. This signal is 3.3 V.
11. For the Coppermine-T differential clock, this signal has been redefined to 2.0 V tolerant.
1. See
2. The BR0# pin is the only BREQ# signal that is bidirectional. See
3. These signals are specified for Vcc
4. These signals are 2.5 V tolerant.
5. V
6. RESET# must always be terminated to V
7. This signal is not supported by all processors. Refer to the Pentium
8. This signal is used to control the value of the processor on-die termination resistance. Refer to the platform
9. These signals are also classified as AGTL. Refer to the Pentium
System Bus
Clock
(1.25 V/2.5 V)
APIC Clock
(2.0 V)
APIC I/O
Power/Other
internal BREQ# signals are mapped onto the BR[1:0]# pins after the agent ID is determined.
VID[3:0] is described in
V
V
V
BSEL[1:0] is described in
All other signals are described in
signal.
complete listing of processors that support this pin.
design guide for the recommended pull-down resistor value.
complete listing of processors that support the AGTL and AGTL+ specifications.
Group Name
CC CORE
TT
SS
CC
10, 12
1.5
is used to terminate the system bus and generate V
Section 7.0
is system ground.
,
3
V
CC
is the power supply for the processor core and is described in
5
2.5
,
Vcc
for information on the these signals.
CMOS
BCLK, BCLK0#
PICCLK
PICD[1:0]
BSEL[1:0], CLKREF
THERMDN, THERMDP, RTTCTRL
V
CC CORE
Section
are described in
Section 2.8.2
11
, V
REF
2.6.
Section
, V
CMOS
SS
10
, V
and
(1.5 V for the Pentium III processor) operation.
TT
, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL,
Section
7.0.
TT
1
on the motherboard, on-die termination is not provided for this
Section
, Reserved
(Sheet 2 of 2)
2.3.
7.0.
8
, V
REF
CORE DET
Signals
on the motherboard.
®
Section 7.0
III Processor Specification Update for a
, VID[3:0], V
®
III Processor Specification Update for a
Section
for more information. The
CC 1.5
2.6.
,
V
CC 2.5
,
V
CC CMOS
Datasheet
,