pga370 ETC-unknow, pga370 Datasheet - Page 5

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

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Second Level (L2) Cache Implementation ........................................................... 8
AGTL+/AGTL Bus Topology in a Uniprocessor Configuration ............................14
AGTL+/AGTL Bus Topology in a Dual-Processor Configuration ........................14
Stop Clock State Machine ...................................................................................15
Processor Vcc
Differential Clocking Example .............................................................................20
BSEL[1:0] Example for a 100/133 MHz or 100 MHz Only System Design .........25
Slew Rate (23A Load Step).................................................................................33
Generic Clock Waveform ....................................................................................41
BCLK, PICCLK, and TCK Generic Clock Waveform...........................................42
System Bus Valid Delay Timings ........................................................................42
System Bus Setup and Hold Timings..................................................................43
System Bus Reset and Configuration Timings....................................................43
Platform Power-On Sequence Timings ...............................................................44
Power-On Reset and Configuration Timings.......................................................45
BCLK, PICCLK Generic Clock Waveform at the Processor Pins........................47
Low to High AGTL+ Receiver Ringback Tolerance.............................................48
Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform .......................53
Maximum Acceptable AGTL Overshoot/Undershoot Waveform .........................53
Non-AGTL+ (Non-AGTL) Overshoot/Undershoot, Settling Limit, and
Ringback 1 ..........................................................................................................54
Processor Functional Die Layout for FC-PGA.....................................................58
FC-PGA and FC-PGA2 Package Types .............................................................60
Package Dimensions...........................................................................................61
Package Dimensions for FC-PGA2.....................................................................63
FC-PGA2 Flatness Specification.........................................................................64
Top Side Processor Markings for FC-PGA (up to CPUID 0x686H) ....................65
Top Side Processor Markings for FC-PGA (for CPUID 0x68AH)).......................65
Top Side Processor Markings for FC-PGA2 .......................................................66
Volumetric Keep-Out for FC-PGA and FC-PGA2................................................66
Component Keep-Out .........................................................................................67
Intel
Conceptual Boxed Intel
Dimensions of Mechanical Step Feature in Heatsink Base.................................81
Dimensions of Notches in Heatsink Base ...........................................................82
Thermal Airspace Requirement for all Boxed Intel
Heatsinks in the PGA370 Socket ........................................................................83
Boxed Processor Fan Heatsink Power Cable Connector Description.................84
Motherboard Power Header Placement Relative to the Boxed
Intel
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Pentium
Pentium
Pentium
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CMOS
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III Processor Pinout ...................................................................68
III Processor ..............................................................................84
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Package Routing ................................................................18
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Pentium
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III Processor for the PGA370 Socket ..........80
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Pentium
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III Processor Fan
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