pga370 ETC-unknow, pga370 Datasheet - Page 32

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

Pentium
32
Table 7.
I
I
IV
I
I
I
dI
dI
CC
CLKREF
SGnt
SLP
DSLP
®
Symbol
CC
v
TT
TT
CMOS
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
CORE
/dt
/dt
Voltage and Current Specifications
NOTES:
10.The current specified is the current required for a single processor. A similar amount of current is drawn
12.Maximum values are specified by design/characterization at nominal Vcc
13.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum
14.dIcc/dt specifications are measured and specified at the PGA370 socket pins.
15.CLKREF must be held to 1.25 V ±6.5%. This tolerance accounts for a ±5% power supply and ±1% resistor
16.Static voltage regulation includes: DC output initial voltage set point adjust, Output ripple and noise, Output
17.This specification applies to PGA370 processors operating at frequencies of 933 MHz or higher.
11. The current specified is also for AutoHALT state.
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All specifications in this table apply only to the Pentium III processor. For motherboard compatibility with the
3. Vcc
4. Use the “typical voltage” specification with the “tolerance specifications” to provide correct voltage regulation
5. V
6. These are the tolerance requirements, across a 20 MHz frequency bandwidth, measured at the
7. V
8. Maximum I
9. Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output
Celeron processor, see the Intel
to the processor.
held to 1.5 V ±3% while the processor system bus is static (idle condition). The ±3% range is the required
design target; ±9% will come from the transient noise added. This is measured at the PGA370 socket pins on
the bottom side of the baseboard.
processor socket pin on the soldered-side of the motherboard. V
voltage specification within 100 s after a transient event; see the VRM 8.4 DC-DC Converter Design
Guidelines for further details.
Intel
voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of Vcc
(Vcc
the specified maximum current Icc
through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended termination is
used (see
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
divider tolerance. It is recommended that the motherboard generate the CLKREF reference from either the
2.5 V or 3.3 V supply. V
reference.
load ranges specified in the tables above.
TT
REF
I
CLKREF voltage
supply current
Termination voltage
supply current
I
processor core
I
core
I
processor core
Power supply current
slew rate
Termination current
slew rate
CC
CC
CC
CC
CORE
and Vcc
®
CORE_TYP
for Vcc
Stop-Grant for
Sleep for processor
Deep Sleep for
should be generated from V
Pentium
Parameter
and Icc
Section
CC
1.5
CMOS
). In this case, the maximum current level for the regulator, Icc
is measured at V
®
must be held to 1.5 V ±9% while the AGTL+ bus is active. It is required that V
II Processor Developer’s Manual for more details on V
CORE
Icc
2.1).
CORE_REG
supply the processor core and the on-die L2 cache.
TT
should not be used due to risk of AGTL+ switching noise coupling to this analog
Core
Freq
= Icc
CC
Processor
®
TT
Celeron
CORE _MAX
typical voltage and under a maximum signal loading conditions.
CORE_MAX
by a voltage divider of 1% resistors or 1% matched resistors. Refer to the
CPUID
TM
1, 2
Processor Datasheet.
and is calculated by the equation:
(Vcc
(Sheet 5 of 5)
Min
CORE_TYP
Typ
- Vcc
CORE_STATIC_TOLERANCE
CC CORE
Max
250
240
REF
2.7
6.9
6.9
6.6
60
8
CORE
.
CORE_REG
must return to within the static
.
Unit
A/µs
A/µs
mA
µA
A
A
A
A
, can be reduced from
12, 13, See
12, 13, 14
Table 12
Notes
TT
) / Vcc
8, 11
10
8
8
and Vcc
Datasheet
CORE_TYP
CORE
1.5
be