pga370 ETC-unknow, pga370 Datasheet - Page 42

• Manufacturer Part Number: pga370
• Description: Mpu Pentium Iii 64-bit 0.18um 700mhz 370-pin Fcpga
• Manufacturer: ETC-unknow

Pentium
42
Figure 10. BCLK, PICCLK, and TCK Generic Clock Waveform
Figure 11. System Bus Valid Delay Timings
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
T
T
T
T
T
V1 = B CLK is referenced to 0.30V (D ifferential M ode), 0.50V (Single-Ended M ode)
V2 = B CLK is refernced to 0.9V (Differental M ode), 2.0V (Single-E nded M ode)
V3 = B CLK and BLCK # crossing point of the rising edge of BLCK and the falling edge of BCLK# (Differential M ode),
r
f
h
l
p
= T3, T23, T32, (High Tim e)
= T1, T22, T31 (BC LK, TCK, PIC CLK Period)
= T6, T26, T35, (Fall Tim e)
= T4, T24, T33, (Low Tim e)
= T5, T25, T34, (Rise Tim e)
BCLK#
BCLK
Signal
TCK is referenced to Vref - 200 m V, PICC LK is referenced to 0.4V.
TCK is referenced to Vref + 200 m V, PICC LK is refernced to 1.6V
BCLK i refereced to 1.25V (Single-Ended M ode), PIC CLK is reference to 1.0V, TCK is referenced to Vcm osref
Tx = T7, T11, T29a, T29b (Valid Delay)
Tpw = T14, T15 (Pulse Width)
V = Vref for AGTL signal group; Vcmosref for CMOS, APIC and TAP signal groups
Vringback
Vringback
(rise)
(fall)
0V
Tx
T
h
V
T
T
f
p
Vih diff
Valid
NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BCLK and BCLK#
T
l
Tpw
Valid
T
r
Vil diff
Tx
V2
V3
V1
Datasheet