at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 228

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Data Transfer
SS Management
228
AT85C51SND3B
The Clock Polarity bit (CPOL in SPCON) defines the default SCK line level in idle
state
input data are sampled and the edges on which the output data are shifted (see
Figure 119 and Figure 120).
For simplicity, Figure 119 and Figure 120 depict the SPI waveforms in idealized form
and do not provide precise timing information. For timing parameters refer to the
Section “AC Characteristics”, page 247.
Note:
Figure 119. Data Transmission Format (CPHA = 0, UARTM = 0)
Figure 120. Data Transmission Format (CPHA = 1, UARTM = 0)
Figure 119 shows a SPI transmission with CPHA = 0, where the first SCK edge is the
MSB capture point. Therefore the slave starts to output its MSB as soon as it is
selected: SS asserted to low level. SS must then be de-asserted between each byte
transmission (see Figure 121). SPDAT must be loaded with a data before SS is
asserted again.
Note:
MOSI (From Master)
MOSI (from master)
SCK Cycle Number
MISO (From Slave)
SCK cycle number
MISO (from slave)
SCK (CPOL = 0)
SCK (CPOL = 1)
SCK (CPOL = 0)
SCK (CPOL = 1)
SPEN (internal)
SPEN (Internal)
(1)
Capture point
Capture point
SS (to slave)
SS (to slave)
while the Clock Phase bit (CPHA in SPCON) defines the edges on which the
1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.
In master mode, SPI transmission with CPHA = 0 is not allowed in case of DFC transfer.
MSB
MSB
MSB
MSB
1
1
bit 6
bit 6
bit 6
bit 6
2
2
bit 5
bit 5
bit 5
bit 5
3
3
bit 4
bit 4
bit 4
bit 4
4
4
bit 3
bit 3
bit 3
bit 3
5
5
bit 2
bit 2
bit 2
bit 2
6
6
bit 1
bit 1
bit 1
bit 1
7
7
LSB
LSB
LSB
8
8
7632C–MP3–11/06
LSB