at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 205

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

7632C–MP3–11/06
Reset Value = 0000 0000b
Table 226. MMSTA Register
MMSTA (1.B5h Read Only) – MMC Status Register
Reset Value = XX00 0000b, depends wether a card is present in the socket or not and if
it is locked or not.
Number
Number
SDWP
7-0
Bit
Bit
7
7
6
5
4
3
2
1
0
Mnemonic Description
Mnemonic Description
BLEN7:0
CRC16S
CBUSY
CRC7S
DATFS
SDWP
WFRS
CDET
CDET
HFRS
Bit
Bit
6
Block Length LSB
Refer to Table 221 for byte description
SD Card Write Protect Bit
Set by hardware when the SD card socket WP switch is opened.
Cleared by hardware when the SD card socket WP switch is closed.
Card Detection Bit
Set by hardware when the SD card socket presence switch is opened.
Cleared by hardware when the SD card socket presence switch is closed.
Card Busy Flag
Set by hardware when the card sends a busy state on the data line.
Cleared by hardware when the card no more sends a busy state on the data line.
CRC16 Status Bit
Transmission mode
Set by hardware when the token response reports a bad CRC.
Cleared by software by setting DCR bit in MMCON2.
Reception mode
Set by hardware when the CRC16 received in the data block is not correct.
Cleared by software by setting DCR bit in MMCON2.
Data Format Status Bit
Transmission mode
Set by hardware when the format of the token response is correct.
Cleared by hardware when the format of the token response is not correct.
Reception mode
Set by hardware when the format of the frame is correct.
Cleared by hardware when the format of the frame is not correct.
CRC7 Status Bit
Set by hardware when the CRC7 computed in the response is correct.
Cleared by hardware when the CRC7 computed in the response is not correct.
This bit is not relevant when CRCDIS is set.
Whole FIFO Ready Status Bit
Set by hardware when 16 bytes can be read in receive mode or written in
transmit mode.
Cleared by hardware when FIFO is not ready.
Half FIFO Ready Status Bit
Set by hardware when 8 bytes can be read in receive mode or written in transmit
mode.
Cleared by hardware when FIFO is not ready.
CBUSY
5
CRC16S
4
DATFS
3
AT85C51SND3B
CRC7S
2
WFRS
1
HFRS
0
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