at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 226

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Slave Mode
226
AT85C51SND3B
The transmission begins by writing to SPDAT through CPU or DFC. Writing to SPDAT
writes to an intermediate register which is automatically loaded to the shift register if no
transmission is in progress. Reading SPDAT through CPU or DFC reads an intermedi-
ate register updated at the end of each transfer.
The byte begins shifting out on the MOSI pin under the control of the bit rate generator.
This generator also controls the shift register of the slave peripheral through the SCK
output pin. As the byte shifts out, another byte shifts in from the slave peripheral on the
MISO pin. The byte is transmitted most significant bit (MSB) first when UARTM bit in
SPCR is cleared or least significant bit (LSB) first when UARTM bit in SPCR is set. The
end of transfer is signaled by SPIF being set.
In case SPI is the source of a DFC channel (slave device data read), SPDAT is first
loaded with a dummy byte (FFh value) to initiate the transfer. Then transfer continues by
transmitting the shift register content which is the last data received.
When the AT85C51SND3B is the only master on the bus, it can be useful not to use SS
pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON.
Figure 117. SPI Master Mode Block Diagram
Note:
The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has
been loaded in SPDAT.
Note:
Figure 118 shows the SPI block diagram in slave mode. In slave mode, before a data
transmission occurs, the SS pin of the slave SPI must be asserted to low level. SS must
remain low until the transmission of the byte is complete. In the slave SPI module, data
enters the shift register through the MOSI pin under the control of the serial clock pro-
vided by the master SPI module on the SCK input pin. When the master starts a
transmission, the data in the shift register begins shifting out on the MISO pin. The end
of transfer is signaled by SPIF being set.
MOSI/P3.1
MISO/P3.0
CLOCK
SCK/P3.2
PER
SS/P3.3
MSTR bit in SPCON is set to select master mode.
The SPI Module should be configured as a slave before it is enabled (SPEN set).
SPCON.6
SPEN
SPCON.5
SSDIS
Generator
SPR2:0
Bit Rate
SPCON
SPCON.2
CPHA
Clock Logic
Control
and
SPCON.3
CPOL
I
SPSCR.4
SPSCR.6
SPSCR.7
SPSCR.3
UARTM
MODF
SPSCR.2
SPTE
SPIF
OVR
8-bit Shift Register
SPDAT WR
SPDAT RD
7632C–MP3–11/06
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