at85c51snd3b ATMEL Corporation, at85c51snd3b Datasheet - Page 196

• Manufacturer Part Number: at85c51snd3b
• Description: Single-chip Digital Audio Decoder - Encoder With Usb 2.0 Interface
• Manufacturer: ATMEL Corporation

Data Configuration
Data Transmitter
Configuration
DFC Data Loading
C51 Data Loading
196
AT85C51SND3B
Before sending or receiving any data, the data line controller must be configured accord-
ing to the type of the data transfer considered. This is achieved using the Data Format
bit: DFMT in MMCON0 register. Clearing DFMT bit enables the data stream format
while setting DFMT bit enables the data block format. In data block format, the single or
multi-block mode must also be configured by clearing or setting the MBLOCK bit in
MMCON0 register and the block length in bytes using BLEN11:0
MMBLP according to Table 221. Figure 90 summarizes the data modes configuration
flows. BLEN can have any value between 1 to 2048.
Table 221. Block Length Programming
Note:
Figure 90. Data Controller Configuration Flows
For transmitting data to the card the data controller must be configured in transmission
mode by setting the DATDIR bit in MMCON1 register.
Figure 91 summarizes the data stream transmission flows in both polling and interrupt
modes while Figure 92 summarizes the data block transmission flows in both polling
and interrupt modes, these flows assume that block length is greater than 16 Bytes.
In case the data transfer is handled by the DFC, a DFC channel must be configured with
the MMC controller as destination peripheral. The programmed number of data is auton-
omously transferred from the source peripheral to the FIFO without any intervention
from the firmware.
In case both FIFO are empty (e.g. source peripheral busy), card clock is automatically
frozen stopping card data transfer thanks to the controller automatic flow control.
In case the data transfer is handled by the C51
FIFO by writing to MMDAT register. Number of data loaded may vary from 1 to 16
Bytes. Then if necessary (more than 16 Bytes to send) software must ensure that all
FIFO or half FIFO becomes empty (WFRS or HFRS set) before loading 16 or 8 new
data.
In case both FIFO are empty, card clock is automatically frozen stopping card data
transfer thanks to the controller automatic flow control.
Note:
1. BLEN = 1to 2048
1. An enabled DFC transfer always takes precedence on a C51 transfer, it is under soft-
MMCON1.7:4
MMBLP7:0
Register
Configure Format
ware responsibility not to write to MMDAT register while a DFC transfer is enabled.
Configuration
Data Stream
DFMT = 0
Description
Block Size LSB: BLEN11:8
Block Size MSB (LSN): BLEN7:0
Data Single Block
Configure Format
BLEN11:0 = XXXh
Configuration
MBLOCK = 0
DFMT = 1
(1)
, data is loaded byte by byte in the
Data Multi-Block
Configure Format
BLEN11:0 = XXXh
Configuration
(1)
MBLOCK = 1
DFMT = 1
bits in MMCON1 and
7632C–MP3–11/06