isp1564 NXP Semiconductors, isp1564 Datasheet - Page 65

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 99.
Address: Content of the base address register + 20h
[1]
Table 100. USBCMD - USB Command register bit description
Address: Content of the base address register + 20h
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 24
23 to 16
15 to 8
7
The reserved bits must always be written with the reset value.
Symbol
reserved
ITC[7:0]
reserved
LHCR
USBCMD - USB Command register bit allocation
LHCR
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Description
-
Interrupt Threshold Control: Default = 08h. This field is used by the system software to select the
maximum rate at which the Host Controller will issue interrupts. If software writes an invalid value to
this register, the results are undefined. Valid values are:
00h — reserved
01h — 1 microframe
02h — 2 microframes
04h — 4 microframes
08h — 8 microframes (equals 1 ms)
10h — 16 microframes (equals 2 ms)
20h — 32 microframes (equals 4 ms)
40h — 64 microframes (equals 8 ms)
Software modifications to this field while HCH (bit 12) in the USBSTS register is zero results in
undefined behavior.
-
Light Host Controller Reset: This control bit is not required. It allows the driver software to reset
the EHCI controller, without affecting the state of the ports or the relationship to the companion Host
Controllers. If not implemented, a read of this field will always return zero. If implemented, on read:
0 — Indicates that the Light Host Controller Reset has completed and it is ready for the host
software to re-initialize the Host Controller.
1 — Indicates that the Light Host Controller Reset has not yet completed.
IAAD
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
R/W
R/W
R/W
ASE
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 4 December 2006
PSE
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
ITC[7:0]
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
0
1
0
3
0
FLS[1:0]
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
HS USB PCI Host Controller
RESET
R/W
R/W
R/W
R/W
HC
25
17
0
0
9
0
1
0
© NXP B.V. 2006. All rights reserved.
ISP1564
R/W
R/W
R/W
R/W
RS
24
16
0
0
8
0
0
0
65 of 99