isp1564 NXP Semiconductors, isp1564 Datasheet - Page 38

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 52.
Address: Content of the base address register + 04h
Table 53.
Address: Content of the base address register + 08h
ISP1564_1
Product data sheet
Bit
4
3
2
1 to 0
Bit
Symbol
Reset
Access
Symbol
CLE
IE
PLE
CBSR
[1:0]
HcControl - Host Controller Control register bit description
HcCommandStatus - Host Controller Command Status register bit allocation
11.1.3 HcCommandStatus register
R/W
31
0
Description
Control List Enable: This bit is set to enable the processing of the control list in the next frame. If
cleared by the HCD, processing of the control list does not occur after the next SOF. The Host
Controller must check this bit whenever it wants to process the list. When disabled, the HCD may
modify the list. If HcControlCurrentED is pointing to an ED to be removed, the HCD must advance
the pointer by updating HcControlCurrentED before re-enabling processing of the list.
Isochronous Enable: This bit is used by the HCD to enable or disable processing of isochronous
EDs. While processing the periodic list in a frame, the Host Controller checks the status of this bit
when it finds an isochronous ED (F = 1). If set (enabled), the Host Controller continues processing
EDs. If cleared (disabled), the Host Controller halts processing of the periodic list, which now
contains only isochronous EDs, and begins processing bulk or control lists. Setting this bit is
guaranteed to take effect in the next frame and not the current frame.
Periodic List Enable: This bit is set to enable the processing of the periodic list in the next frame. If
cleared by the HCD, processing of the periodic list does not occur after the next SOF. The Host
Controller must check this bit before it starts processing the list.
Control Bulk Service Ratio: This specifies the service ratio of control EDs over bulk EDs. Before
processing any of the nonperiodic lists, the Host Controller must compare the ratio specified with its
internal count on how many nonempty control EDs are processed, in determining whether to
continue serving another control ED or switching to bulk EDs. The internal count must be retained
when crossing the frame boundary. After a reset, the HCD is responsible to restore this value.
00b — 1 : 1
01b — 2 : 1
10b — 3 : 1
11b — 4 : 1
The HcCommandStatus register is used by the Host Controller to receive commands
issued by the HCD. It also reflects the current status of the Host Controller. To the HCD, it
appears as a ‘write to set’ register. The Host Controller must ensure that bits written as
logic 1 become set in the register while bits written as logic 0 remain unchanged in the
register. The HCD may issue multiple distinct commands to the Host Controller without
concern for corrupting previously issued commands. The HCD has normal read access to
all bits.
The SOC[1:0] field (bits 17 and 16 in the HcCommandStatus register) indicates the
number of frames with which the Host Controller has detected the scheduling overrun
error. This occurs when the periodic list does not complete before EOF. When a
scheduling overrun error is detected, the Host Controller increments the counter and sets
SO (bit 0 in the HcInterruptStatus register).
Table 53
R/W
30
0
shows the bit allocation of the HcCommandStatus register.
R/W
29
0
Rev. 01 — 4 December 2006
R/W
28
0
reserved
[1]
R/W
27
0
…continued
R/W
26
0
HS USB PCI Host Controller
R/W
25
0
© NXP B.V. 2006. All rights reserved.
ISP1564
R/W
24
0
38 of 99