isp1564 NXP Semiconductors, isp1564 Datasheet - Page 58

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 90.
Address: Content of the base address register + 50h
Table 91.
Address: Content of the base address register + 54h
[1]
ISP1564_1
Product data sheet
Bit
14 to 2
1
0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits must always be written with the reset value.
Symbol
reserved
OCI
LPS
HcRhStatus - Host Controller Root Hub Status register bit description
HcRhPortStatus[2:1] - Host Controller Root Hub Port Status[2:1] register bit allocation
11.1.22 HcRhPortStatus[2:1] register
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Description
-
Overcurrent Indicator: This bit reports overcurrent conditions when global reporting is implemented.
When set, an overcurrent condition exists. When cleared, all power operations are normal. If the
per-port overcurrent protection is implemented, this bit is always logic 0.
On read Local Power Status: The root hub does not support the local power status feature.
Therefore, this bit is always read as logic 0.
On write Clear Global Power: In global power mode (Power Switching Mode = 0), logic 1 is written to
this bit to turn off power to all ports (clear Port Power Status). In per-port power mode, it clears Port
Power Status only on ports whose Port Power Control Mask bit is not set. Writing logic 0 has no
effect.
The HcRhPortStatus[2:1] register is used to control and report port events on a per-port
basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that
are implemented in hardware. The lower word reflects the port status. The upper word
reflects status change bits. Some status bits are implemented with special write behavior.
If a transaction, token through handshake, is in progress when a write to change port
status occurs, the resulting port status change is postponed until the transaction
completes. Always write logic 0 to the reserved bits. The bit allocation of the register is
given in
reserved
reserved
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Table
[1]
[1]
91.
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 4 December 2006
reserved
[1]
PRSC
PRS
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
[1]
OCIC
POCI
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
PSSC
…continued
PSS
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
HS USB PCI Host Controller
PESC
LSDA
R/W
R/W
R/W
PES
R/W
25
17
0
0
9
0
1
0
© NXP B.V. 2006. All rights reserved.
ISP1564
CSC
CCS
PPS
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0
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