isp1564 NXP Semiconductors, isp1564 Datasheet - Page 53

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 81.
Address: Content of the base address register + 40h
[1]
Table 82.
Address: Content of the base address register + 40h
Table 83.
Address: Content of the base address register + 44h
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 14
13 to 0
Bit
Symbol
Reset
Access
The reserved bits must always be written with the reset value.
Symbol
reserved
P_S[13:0]
HcPeriodicStart - Host Controller Periodic Start register bit allocation
HcPeriodicStart - Host Controller Periodic Start register bit description
HcLSThreshold - Host Controller Low-Speed Threshold register bit allocation
11.1.17 HcPeriodicStart register
11.1.18 HcLSThreshold register
R/W
R/W
R/W
R/W
R/W
31
23
15
31
0
0
0
7
0
0
reserved
This register has a 14-bit programmable value that determines when is the earliest time
for the Host Controller to start processing the periodic list. For bit allocation, see
This register contains an 11-bit value used by the Host Controller to determine whether to
commit to the transfer of a maximum of 8-byte low-speed packet before EOF. Neither the
Host Controller nor the HCD can change this value. For bit allocation, see
Description
-
Periodic Start: After a hardware reset, this field is cleared. It is then set by the HCD during the
Host Controller initialization. The value is roughly calculated as 10 % of HcFmInterval. A typical
value is 3E67h. When HcFmRemaining reaches the value specified, processing of the periodic
lists have priority over control or bulk processing. The Host Controller, therefore, starts processing
the interrupt list after completing the current control or bulk transaction that is in progress.
[1]
R/W
R/W
R/W
R/W
R/W
30
22
14
30
0
0
0
6
0
0
R/W
R/W
R/W
R/W
R/W
29
21
13
29
0
0
0
5
0
0
Rev. 01 — 4 December 2006
R/W
R/W
R/W
R/W
R/W
28
20
12
28
0
0
0
4
0
0
reserved
reserved
reserved
P_S[7:0]
[1]
[1]
[1]
R/W
R/W
R/W
R/W
R/W
27
19
11
27
0
0
0
3
0
0
P_S[13:8]
R/W
R/W
R/W
R/W
R/W
26
18
10
26
0
0
0
2
0
0
HS USB PCI Host Controller
R/W
R/W
R/W
R/W
R/W
25
17
25
0
0
9
0
1
0
0
© NXP B.V. 2006. All rights reserved.
ISP1564
Table
83.
Table
R/W
R/W
R/W
R/W
R/W
24
16
24
0
0
8
0
0
0
0
53 of 99
81.