isp1564 NXP Semiconductors, isp1564 Datasheet - Page 28

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 37.
Table 38.
Address: Value read from address 34h + 6h
Table 39.
Address: Value read from address 34h + 6h
ISP1564_1
Product data sheet
Bit
8
7 to 2
1 to 0
Bit
Symbol
Reset
Access
Bit
7
6
5 to 0
Address: Value read from address 34h + 4h
Symbol
BPCC_EN Bus Power or Clock Control Enable:
B2_B3#
reserved
PMCSR - Power Management Control/Status register bit description
PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit allocation
PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit description
Symbol
PMEE
reserved
PS[1:0]
8.2.3.5 PMCSR_BSE register
BPCC_EN
R
7
0
Description
1 — Indicates that the bus power or clock control mechanism as defined in
0 — Indicates that the bus power or control policies as defined in
When the bus power or clock control mechanism is disabled, the bridge’s PMCSR Power State (PS)
field cannot be used by the system software to control the power or clock of the bridge’s secondary
bus.
B2 or B3 support for D3
result of programming the function to D3
1 — Indicates that when the bridge function is programmed to D3
be stopped (B2).
0 — Indicates that when the bridge function is programmed to D3
power removed (B3).
This bit is only meaningful if bit 7 (BPCC_EN) is logic 1.
-
The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI
bridge-specific functionality and is required for all PCI-to-PCI bridges. The bit allocation of
this register is given in
Description
PME Enabled: Logic 1 allows the function to assert PME#. When it is logic 0, PME# assertion is
disabled. This bit defaults to logic 0, if the function does not support the PME# generation from
D3
cleared by the operating system each time the operating system is initially loaded.
-
Power State: This two-bit field is used to determine the current power state of the EHCI function
and to set the function into a new power state. The definition of the field values is given as:
00b — D0
01b — D1
10b — D2
11b — D3
If the software attempts to write an unsupported, optional state to this field, the write operation
must complete normally on the bus; however, data is discarded and no status change occurs.
cold
B2_B3#
. If the function supports PME# from D3
R
6
0
hot
R
hot
5
0
Rev. 01 — 4 December 2006
: The state of this bit determines the action that is to occur as a direct
Table
38.
R
4
0
hot
.
cold
R
3
0
, then this bit is sticky and must explicitly be
reserved
…continued
hot
Table 40
hot
R
, its secondary bus’s PCI clock will
2
0
, its secondary bus will have its
HS USB PCI Host Controller
are disabled.
Table 40
R
1
0
© NXP B.V. 2006. All rights reserved.
ISP1564
is enabled.
R
0
0
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