mc68hc908mr32 Freescale Semiconductor, Inc, mc68hc908mr32 Datasheet - Page 72

• Manufacturer Part Number: mc68hc908mr32
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
The K factor in the equations is derived from internal PLL parameters. K
is configured in acquisition mode, and K
See
In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the
reference frequency. See
cycles, n
before exiting acquisition mode. A certain number of clock cycles, n
PLL is within the lock mode entry tolerance, ∆
multiple of n
the average frequency over the entire measurement period must be within the specified tolerance, the
total time usually is longer than t
In manual mode, it is usually necessary to wait considerably longer than t
clock (see
Influences on Reaction Time
72
4.3.2.2 Acquisition and Tracking
ACQ
4.3.3 Base Clock Selector
ACQ
, is required to ascertain that the PLL is within the tracking mode entry tolerance, ∆
The inverse proportionality between the lock time and the reference
frequency.
/f
RDV
, and the acquisition to lock time, t
4.3.2.3 Manual and Automatic PLL Bandwidth Modes
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
may slow the lock time considerably.
Lock
as calculated in the previous example.
Modes.
Circuit) because the factors described in
TRK
t
ACQ
t
AL
t
Lock
is the K factor when the PLL is configured in tracking mode.
=
Lock
=
⎛
⎜
⎝
⎛
⎜
⎝
V
-------------- -
=
NOTE
f
V
-------------- -
. Therefore, the acquisition time, t
RDV
f
DDA
RDV
DDA
t
ACQ
⎞
⎟
⎠
AL
⎞
⎟
⎠
⎛
⎝
⎛
⎝
------------- -
K
+
-------------- -
K
, is an integer multiple of n
TRK
t
4
ACQ
AL
8
⎞
⎠
⎞
⎠
TRK
ACQ
, is required to ascertain that the
Lock
is the K factor when the PLL
before selecting the PLL
A certain number of clock
4.8.2 Parametric
TRK
Freescale Semiconductor
ACQ
/f
, is an integer
RDV
. Also, since
TRK
,