mc68hc908mr32 Freescale Semiconductor, Inc, mc68hc908mr32 Datasheet - Page 65

• Manufacturer Part Number: mc68hc908mr32
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.4.6 Crystal Output Frequency Signal (CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (f
directly from the crystal oscillator circuit.
and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may
depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.
4.4.7 CGM Base Clock Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks.
CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK,
divided by two.
4.4.8 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
4.5 CGM Registers
These registers control and monitor operation of the CGM:
Figure 4-4
Freescale Semiconductor
$005C
$005D
$005E
Notes:
Addr.
•
•
•
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
PLL control register (PCTL) — see
PLL bandwidth control register (PBWC) — see
PLL programming register (PPG) — see
is a summary of the CGM registers.
PLL Bandwidth Control Register
Register Name
PLL Programming Register
PLL Control Register
See page 66.
See page 67.
See page 68.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
(PBWC)
(PCTL)
(PPG)
Figure 4-4. CGM I/O Register Summary
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Figure 4-3
4.5.1 PLL Control Register
PLLIE
AUTO
MUL7
Bit 7
R
0
0
0
4.5.3 PLL Programming Register
= Reserved
LOCK
MUL6
shows only the logical relation of CGMXCLK to OSC1
PLLF
R
R
6
0
0
1
4.5.2 PLL Bandwidth Control Register
PLLON
MUL5
ACQ
5
1
0
1
MUL4
BCS
XLD
4
0
0
0
VRS7
R
R
3
1
1
0
0
0
VRS6
R
R
2
1
1
0
0
1
XCLK
VRS5
CGM Registers
) and comes
R
R
1
1
1
0
0
1
VRS4
Bit 0
R
R
1
1
0
0
0
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